Layout Techniques in MOSFETs / by Salvador Pinillos Gimenez
By: Gimenez, Salvador Pinillos,, autor
Material type:
E-bookSeries: (Synthesis Lectures on Emerging Engineering Technologies, 2381-1439).Publisher: Cham : Springer International Publishing, 2016Edition: 1st edition 2016.Description: 1 recurso en línea (XI, 69 páginas).ISBN: 9783031020315.Subject: Semiconductores
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | |
|---|---|---|---|---|---|---|---|---|
LIBRO-E NO PRÉSTAMO
|
Madrid Digital Acceso Electrónico (UEM) | Ciencias e Ingeniería | TK7871.95 2016 EB (Browse shelf(Opens below)) | Acceso electrónico | eBook.01113074 |
Browsing Madrid Digital shelves, Shelving location: Acceso Electrónico (UEM) Close shelf browser (Hides shelf browser)
| TK7871.89.L53 .G87 2017 EB Light emitting diodes for agriculture : smart lighting | TK7871.89.L53 S655 2018 EB Solid State Lighting Reliability Part 2 Components to Systems | TK7871.9 2021 EB Highly Integrated Gate Drivers for Si and GaN Power Transistors | TK7871.95 2016 EB Layout Techniques in MOSFETs | TK7871.95 2021 EB Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs | TK7871.95 2022 EB RF and Time-domain Techniques for Evaluating Novel Semiconductor Transistors | TK7871.95 2022 EB Advanced SPICE Model for GaN HEMTs (ASM-HEMT) : A New Industry-Standard Compact Model for GaN-based Power and RF Circuit Design |
Dedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (".
This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
There are no comments on this title.