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001			96108
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008			170602s2017 sz ob 000 0 eng d
020			_a3319570331 _q(electronic bk.)
020			_a9783319570334 _q(electronic bk.)
020			_z3319570323
020			_z9783319570327
040			_aYDX _cYDX _dN$T _dEBLCP _dN$T _dGW5XE _dUAB _dESU _dAZU _dUPM _dOCLCF _dIOG _dCOO _dMERER _dOCLCQ _dIDB _dU3W _dMERUC _dES-MaUEC _bspa
050		4	_aTK7872.M6 _bF688 2017 EB
066			_c(S
100	1		_aFouto, David.
245	1	0	_aDesign of low power and low area passive sigma delta modulators for audio applications _cDavid Fouto, Nuno Paulino.
264		1	_aCham _bSpringer _c2017.
300			_a1 recurso en línea
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF
490	0		_aSpringerBriefs in electrical and computer engineering
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
504			_aIncluye referencias bibliográficas
505	0		_6880-01 _aPreface; Contents; Acronyms; 1 Introduction; 1.1 Motivation and Background; 1.2 Book Organization; 2 Sigma-Delta Modulation; 2.1 Introduction; 2.2 First Order Sigma-Delta Modulator; 2.3 Second Order Sigma-Delta Modulator; 2.4 Higher Order Sigma-Delta Modulator; 2.4.1 The MASH Structure; 3 Architecture and High Level Model; 3.1 Passive Integrator; 3.1.1 Ultra Incomplete Settling; 3.1.2 Discrete Time Transfer Function of the SC Integrator; 3.1.3 Thermal Noise Analysis; 3.2 Modulator Block Diagram; 3.2.1 Signal and Noise Transfer Functions; 3.3 Proposed Architecture; 3.4 High Level Model.
650		7	_aCircuitos eléctricos _2embne _0(OCoLC)fst00904545 _0 _9139226
700	1		_aPaulino, Nuno.
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-57033-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
880			_6520-00/(S _aThis book presents the study, design, modulation, optimization and implementation of low power, passive DT-ΣΔMs for use in audio applications. The high gain and bandwidth amplifier normally used for integration in ΣΔ modulation, is replaced by passive, switched-capacitor branches working under the Ultra Incomplete Settling (UIS) condition, leading to a reduction of the consumed power. The authors describe a design process that uses high level models and an optimization process based in genetic algorithms to achieve the desired performance.
880	8		_6505-01/(S _a3.5 Optimization3.6 Reducing the Size of the Capacitors; 4 Electrical Circuits and Simulation Results; 4.1 Introduction; 4.2 Digital Circuitry; 4.2.1 Logic Gates; 4.2.2 Delay Circuits; 4.2.3 Phase Generator; 4.2.4 Flip-Flop; 4.3 Amplifiers; 4.3.1 Gain G2; 4.3.2 Gain Gmid; 4.4 Comparator; 4.5 Switching Circuitry; 4.5.1 Clock Bootstrapped Switch; 4.6 Feedback and Reference Voltages; 4.7 Monostable Circuit; 4.8 Simulation Results; 4.8.1 Second Order ΣΔ Modulator; 4.8.2 Third Order MASH ΣΔ Modulator; 4.8.3 Third Order MASH ΣΔM with Monostable Circuit; 5 Conclusions; 5.1 Final Remarks; References.
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017D
998			_b02/2018 _dz _e- _zSI
999			_c96108 _d96108 _x1