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008			170426s2017 sz a o 000 0 eng d
020			_a331954313X _q(electronic bk.)
020			_a9783319543130 _q(electronic bk.)
020			_z3319543121
020			_z9783319543123 _q(print)
040			_aN$T _cN$T _dGW5XE _dN$T _dEBLCP _dYDX _dAZU _dUPM _dOCLCF _dVT2 _dUAB _dMERER _dESU _dOCLCQ _dIOG _dOCLCQ _dES-MaUEC _bspa
050		4	_aQA76.87 _bN487 2017 EB
245	0	0	_aNeuro-inspired computing using resistive synaptic devices _cShimeng Yu, editor.
264		1	_aCham, Switzerland _bSpringer _c2017.
300			_a1 recurso en línea (xi, 269 páginas) _bilustraciones (algunas a color)
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
505	0		_aPreface; Acknowledgments; Contents; About the Editor; Chapter 1: Introduction to Neuro-Inspired Computing Using Resistive Synaptic Devices; 1.1 The Demand for New Hardware Beyond von Neumann Architecture; 1.2 Neuromorphic Hardware Accelerators and Why Resistive Synaptic Devices?; 1.3 Desirable Characteristics of Resistive Synaptic Devices; 1.4 Crossbar Array Architecture for Accelerating Weighted Sum and Weight Update; 1.5 Challenges of Mapping Learning Algorithms to Neuromorphic Hardware; References; Part I: Device-Level Demonstrations of Resistive Synaptic Devices.
505	8		_a2.3.3 Ovonic Threshold SwitchReferences; Chapter 3: Pr0.7Ca0.3MnO3 (PCMO)-Based Synaptic Devices; 3.1 Nanoscale PCMO-Based Synaptic Device; 3.2 Reactive Electrode Dependence of PCMO-Based Synaptic Device; 3.3 Nitrogen Treatment for Tunable Synaptic Characteristics; 3.4 Approaches to Improve Synaptic Characteristics; 3.5 Summary and Outlook; References; Chapter 4: TaOx-/TiO2-Based Synaptic Devices; 4.1 Device Fabrication Method; 4.2 Basic Device Characteristics; 4.3 Switching Mechanism; 4.3.1 Experimental Findings; 4.3.2 Physical Modeling; 4.4 Synaptic Function Realization and Modeling Results.
505	8		_a4.4.1 Potentiation and Depression4.4.2 Spike-Timing-Dependent Plasticity; 4.4.3 Paired-Pulse Facilitation; 4.5 3D Synaptic Network; 4.5.1 3D Synaptic Network Realization; 4.5.2 Linearity Tuning; 4.6 Summary and Outlook; References; Part II: Array-Level Demonstrations of Resistive Synaptic Devices and Neural Networks; Chapter 5: Training and Inference in Hopfield Network Using 10x10 Phase Change Synaptic Array; 5.1 Introduction; 5.2 Phase Change Memory Array for Synaptic Operation; 5.3 Hebbian Learning in Synaptic Array.
505	8		_a5.4 Effects of Device-to-Device Variation on Associative Learning Performance5.5 Summary; References; Chapter 6: Experimental Demonstration of Firing Rate Neural Networks Based on Metal-Oxide Memristive Crossbars; 6.1 Introduction; 6.2 Memristive Devices and Crossbar Circuits; 6.2.1 Device Fabrication and Forming; 6.2.2 Dynamic Characteristics; 6.3 Single-Layer Perceptron; 6.3.1 Inference; 6.3.2 Network Training; 6.4 Multilayer Perceptron; 6.5 3D Memristor-CMOS Hybrid Circuits; 6.6 Challenges and Future Work; References.
505	8		_aChapter 2: Synaptic Devices Based on Phase-Change Memory2.1 PCM Basics for Synaptic Devices; 2.1.1 Device Operation; 2.1.2 Phase-Change Materials; 2.1.3 Threshold Switching Mechanism; 2.1.4 Resistance Drift; 2.1.5 Scaling; 2.1.6 Array Architecture and Memory Cell Selector; 2.1.7 Power Consumption; 2.2 PCM Synaptic Device Implementations; 2.2.1 PCM as an Electronic Synapse; 2.2.2 Synaptic Plasticity and Learning; 2.2.3 Pulse Schemes for Plasticity; 2.2.4 Gradual Programming Versus Stochastic Programming; 2.3 Future Outlook; 2.3.1 Resistance State Stability; 2.3.2 New Materials Exploration.
520	3		_aThis book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology." Provides single-source reference to recent breakthroughs in resistive synaptic devices, not only at individual cell-level, but also at integrated array-level; " Includes detailed discussion of the peripheral circuits and array architecture design of the neuro-crossbar system; " Focuses on new experimental results that are likely to solve practical, artificial intelligent problems, such as image classification.
650		7	_aOrdenadores _2embne _0(OCoLC)fst01036251 _0 _9138111
700	1		_aYu, Shimeng _c(Electrical engineer), _eeditor literario
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-54313-0 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017C
998			_b02/2018 _dz _e- _zSI
999			_c95872 _d95872 _x1