| 000 | 05651cam a2200457Ii 4500 | ||
|---|---|---|---|
| 999 |
_c95852 _d95852 _x1 |
||
| 001 | 95852 | ||
| 003 | ES-MaUEC | ||
| 005 | 20230102112724.0 | ||
| 006 | m o d | ||
| 007 | cr cnu|||unuuu | ||
| 008 | 170424s2017 sz a o 000 0 eng d | ||
| 020 |
_a3319548409 _q(electronic bk.) |
||
| 020 |
_a9783319548401 _q(electronic bk.) |
||
| 020 | _z3319548395 | ||
| 020 |
_z9783319548395 _q(print) |
||
| 040 |
_aN$T _cN$T _dGW5XE _dEBLCP _dYDX _dUAB _dN$T _dMERER _dESU _dAZU _dUPM _dOCLCF _dOCLCQ _dOCLCO _dVT2 _dOTZ _dOCLCQ _dIOG _dU3W _dES-MaUEC _bspa |
||
| 050 | 4 |
_aQA76.9.B45 _bE447 2017 EB |
|
| 245 | 0 | 0 |
_aEmerging technology and architecture for big-data analytics _cAnupam Chattopadhyay, Chip Hong Chang, Hao Yu, editors. |
| 264 | 1 |
_aCham, Switzerland _bSpringer _c2017. |
|
| 300 |
_a1 recurso en línea (xi, 330 páginas) _bilustraciones (algunas a color) |
||
| 336 |
_aTexto _btxt _2rdacontent |
||
| 337 |
_aelectrónico _bc _2rdamedia |
||
| 338 |
_arecurso electrónico _bcr _2rdacarrier |
||
| 347 |
_atext file _bPDF _2rda |
||
| 500 | _aSpringerLink | ||
| 505 | 0 | _aPreface; Contents; About the Editors; Part I State-of-the-Art Architectures and Automation for Data-Analytics; 1 Scaling the Java Virtual Machine on a Many-Core System; 1.1 Introduction; 1.2 Background; 1.2.1 Workload Selection; 1.2.2 Performance Analysis Tools; 1.2.3 Experimental Setup; 1.3 Thread-Local Data Objects; 1.4 Memory Allocators; 1.5 Java Concurrency API; 1.6 Garbage Collection; 1.7 Non-uniform Memory Access (NUMA); 1.8 Conclusion and Future Directions; Appendix; References; 2 Accelerating Data Analytics Kernels with HeterogeneousComputing; 2.1 Introduction; 2.2 Motivation. | |
| 505 | 8 | _a2.3 Automated Design Space Exploration Flow2.3.1 The Lin-Analyzer Framework; 2.3.2 Framework Overview; 2.3.3 Instrumentation; 2.3.4 Optimized DDDG Generation; 2.3.4.1 Sub-trace Extraction; 2.3.4.2 DDDG Generation & Pre-optimizations; 2.3.5 DDDG Scheduling; 2.3.6 Enabling Design Space Exploration; 2.4 Acceleration of Data Analytics Kernels; 2.4.1 Estimation Accuracy; 2.4.1.1 Loop Unrolling and Loop Pipelining; 2.4.1.2 Array Partitioning; 2.4.2 Rapid Design Space Exploration; 2.5 Conclusion; References. | |
| 505 | 8 | _a3 Least-squares-solver Based Machine Learning Acceleratorfor Real-time Data Analytics in Smart Buildings3.1 Introduction; 3.2 IoT System Based Smart Building; 3.2.1 Smart-Grid Architecture; 3.2.2 Smart Gateway for Real-Time Data Analytics; 3.2.3 Problem Formulation for Data Analytics; 3.3 Background on Neural Network Based Machine Learning; 3.3.1 Backward Propagation for Training; 3.3.2 Least-Squares Solver for Training; 3.3.3 Feature Extraction with Behavior Cognition; 3.4 Least-Squares Solver Based Training Algorithm; 3.4.1 Regularized 2-Norm; 3.4.2 Square-Root-Free Cholesky Decomposition. | |
| 505 | 8 | _a3.4.3 Incremental Least-Squares Solution3.5 Least-Squares Based Machine Learning Accelerator Architecture; 3.5.1 Overview of Computing Flow and Communication; 3.5.2 FPGA Accelerator Architecture; 3.5.3 2-Norm Solver; 3.5.4 Matrix-Vector Multiplication; 3.6 Experiment Results; 3.6.1 Experiment Setup and Benchmark; 3.6.2 FPGA Design Platform and CAD Flow; 3.6.3 Scalable and Parameterized Accelerator Architecture; 3.6.4 Performance for Data Classification; 3.6.5 Performance for Load Forecasting; 3.6.6 Performance Comparisons with Other Platforms; 3.7 Conclusion; References. | |
| 505 | 8 | _a4 Compute-in-Memory Architecture for Data-Intensive Kernels4.1 Introduction; 4.2 Malleable Hardware Acceleration; 4.2.1 Hardware Architecture; 4.2.2 Application Mapping; 4.2.2.1 Application Description Using an Instruction Set Architecture; 4.2.2.2 Application Mapping to the General Framework; 4.2.3 Domain Customization for Efficient Acceleration; 4.3 Case Studies for Memory-Centric Computing; 4.3.1 MAHA for Security Applications; 4.3.1.1 Domain Exploration; 4.3.1.2 Architecture Description; 4.3.1.3 Results and Comparison to Other Platforms; 4.3.2 MAHA for Text Mining Applications. | |
| 520 | 3 | _aThis book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn't work, and what are the fundamental problems, solutions, upcoming challenges and opportunities. Provides a single-source reference to hardware architectures for big-data analytics; Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems; Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics. | |
| 588 | 0 | _aOnline resource; title from PDF title page (SpringerLink, viewed April 27, 2017). | |
| 988 | _aEBOOK, EBSPRINGER_2017C | ||
| 650 | 7 |
_9495511 _aDatos masivos |
|
| 700 | 1 |
_aChang, Chip-Hong _eeditor literario _996841 |
|
| 700 | 1 |
_aChattopadhyay, Anupam, _eeditor literario |
|
| 700 | 1 |
_aYu, Hao _c(Electrical engineer), _eeditor literario |
|
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-54840-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
_2lcc _cM1S |
||
| 998 |
_b02/2018 _dz _e- _zSI |
||