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008			170215s2017 sz ob 001 0 eng d
020			_a3319534297 _q(electronic bk.)
020			_a9783319534299 _q(electronic bk.)
020			_z3319534289
020			_z9783319534282 _q(print)
035			_a(OCoLC)972640506 _z(OCoLC)972620018 _z(OCoLC)972865267 _z(OCoLC)973015183 _z(OCoLC)973125307 _z(OCoLC)973303241 _z(OCoLC)973381691 _z(OCoLC)973501714 _z(OCoLC)973747701 _z(OCoLC)981816303 _z(OCoLC)1005775391 _z(OCoLC)1012016611
040			_aN$T _cN$T _dIDEBK _dEBLCP _dGW5XE _dN$T _dYDX _dOCLCF _dNJR _dCOO _dIOG _dAZU _dUWO _dUPM _dESU _dZ5A _dJBG _dIAD _dICW _dICN _dOTZ _dOCLCQ _dMERER _dOCLCQ _dU3W _dES-MaUEC _bspa
050		4	_aTK7874 _b.C446 2017 EB
100	1		_aChen, Xiaoming, _eautor
245	1	0	_aParallel sparse direct solver for integrated circuit simulation _cXiaoming Chen, Yu Wang, Huazhong Yang.
264		1	_aCham, Switzerland _bSpringer _c2017
300			_a1 recurso en línea
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
500			_aSpringerLink
504			_aIncluye referencias bibliográficas e índice
505	0		_aPreface; Contents; 1 Introduction; 1.1 Circuit Simulation; 1.1.1 Mathematical Formulation; 1.1.2 LU Factorization; 1.1.3 Simulation Flow; 1.2 Challenges of Parallel Circuit Simulation; 1.2.1 Device Model Evaluation; 1.2.2 Sparse Direct Solver; 1.2.3 Theoretical Speedup; 1.3 Focus of This Book; References; 2 Related Work; 2.1 Direct Parallel Methods; 2.1.1 Parallel Direct Matrix Solutions; 2.1.2 Parallel Iterative Matrix Solutions; 2.2 Domain Decomposition; 2.2.1 Parallel BBD-Form Matrix Solutions; 2.2.2 Parallel Multilevel Newton Methods; 2.2.3 Parallel Schwarz Methods.
505	8		_a2.2.4 Parallel Relaxation Methods2.3 Parallel Time-Domain Simulation; 2.3.1 Parallel Numerical Integration Algorithms; 2.3.2 Parallel Multi-Algorithm Simulation; 2.3.3 Time-Domain Partitioning; 2.3.4 Matrix Exponential Methods; 2.4 Hardware Acceleration Techniques; 2.4.1 GPU Acceleration; 2.4.2 FPGA Acceleration; References; 3 Overall Solver Flow; 3.1 Overall Flow; 3.2 Pre-analysis; 3.2.1 Zero-Free Permutation/Static Pivoting; 3.2.2 Matrix Ordering; 3.2.3 Symbolic Factorization; 3.3 Numerical Full Factorization; 3.3.1 Symbolic Prediction; 3.3.2 Numerical Update; 3.3.3 Partial Pivoting.
505	8		_a3.3.4 Pruning3.4 Numerical Re-factorization; 3.4.1 Factorization Method Selection; 3.5 Right-Hand-Solving; 3.5.1 Forward/Backward Substitutions; 3.5.2 Iterative Refinement; References; 4 Parallel Sparse Left-Looking Algorithm; 4.1 Parallel Full Factorization; 4.1.1 Data Dependence Representation; 4.1.2 Task Scheduling; 4.1.3 Algorithm Flow; 4.1.4 Implementation Details; 4.2 Parallel Re-factorization; 4.2.1 Data Dependence Representation; 4.2.2 Task Scheduling; 4.2.3 Algorithm Flow; 4.2.4 Implementation Details; References; 5 Improvement Techniques; 5.1 Map Algorithm; 5.1.1 Motivation.
505	8		_a5.1.2 Map Definition and Construction5.1.3 Sequential Map Re-factorization; 5.1.4 Parallel Map Re-factorization; 5.2 Supernodal Algorithm; 5.2.1 Motivation; 5.2.2 Supernode Definition and Storage; 5.2.3 Supernodal Full Factorization; 5.2.4 Supernodal Re-factorization; 5.3 Fast Full Factorization; 5.3.1 Motivation and Pivoting Reduction; 5.3.2 Sequential Fast Full Factorization; 5.3.3 Parallel Fast Full Factorization; References; 6 Test Results; 6.1 Experimental Setup; 6.2 Performance Metric; 6.2.1 Speedups; 6.2.2 Performance Profile; 6.3 Results of Benchmark Test.
505	8		_a6.3.1 Comparison of Different Algorithms6.3.2 Relative Speedups; 6.3.3 Speedups; 6.3.4 Other Comparisons; 6.4 Results of Simulation Test; References; 7 Performance Model; 7.1 DAG-Based Performance Model; 7.2 Results and Analysis; 7.2.1 Theoretical Maximum Relative Speedup; 7.2.2 Predicted Relative Speedup; 7.2.3 Bottleneck Analysis; 8 Conclusions; Reference; Index.
520	3		_aThis book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulator and makes circuit simulators more efficient on modern parallel processors; · Uses experimental results from practical applications to demonstrate the performance of the parallel sparse direct solver.
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017B
650		7	_aCircuitos integrados _xComputer simulation. _2embne _0(OCoLC)fst00975537 _0 _9139614
700	1		_aWang, Yu, _eautor _9670932
700	1		_aYang, Huazhong, _eautor
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-53429-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2018 _dz _e- _zSI