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| 100 | 1 |
_aTaraate, Vaibbhav _9100582 |
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| 245 | 1 | 0 |
_aPLD based design with VHDL : _bRTL design, synthesis and implementation _cVaibbhav Taraate. |
| 264 | 1 |
_aSingapore _bSpringer _c2017 |
|
| 300 | _a1 recurso en línea (432 páginas) | ||
| 336 |
_aTexto _btxt _2rdacontent |
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| 337 |
_aelectrónico _bc _2rdamedia |
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| 338 |
_arecurso electrónico _bcr _2rdacarrier |
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| 500 | _aSpringerLink | ||
| 504 | _aIncluye referencias bibliográficas e índice | ||
| 505 | 0 | _aIntroduction to HDL -- Basic Logic Circuits and VHDL Description -- VHDL and Key Important Constructs -- 4 Combinational Logic Design Using VHDL Constructs -- Sequential Logic Design -- Introduction to PLD -- Design and simulation using VHDL constructs -- PLD Based Design Guidelines -- Finite State Machines -- Synthesis Optimization using VHDL -- Design Implementation Using Xilinx Vivado. | |
| 520 | 3 | _aThis book covers basic fundamentals of logic design and advanced RTL design concepts using VHDL. The book is organized to describe both simple and complex RTL design scenarios using VHDL. It gives practical information on the issues in ASIC prototyping using FPGAs, design challenges and how to overcome practical issues and concerns. It describes how to write an efficient RTL code using VHDL and how to improve the design performance. The design guidelines by using VHDL are also explained with the practical examples in this book. The book also covers the ALTERA and XILINX FPGA architecture and the design flow for the PLDs. The contents of this book will be useful to students, researchers, and professionals working in hardware design and optimization. The book can also be used as a text for graduate and professional development courses. | |
| 988 | _aEBOOK, asignarmaterias, EBSPRINGER_2017B | ||
| 650 | 7 |
_aCircuitos integrados _2embne _0(OCoLC)fst00811721 _0 _9139614 |
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_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-981-10-3296-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
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_b02/2018 _dz _e- _zSI |
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