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020			_a3319496794
020			_a9783319496795
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020			_z9783319496788
035			_a(OCoLC)967891292 _z(OCoLC)967512001 _z(OCoLC)967681745 _z(OCoLC)967840338 _z(OCoLC)967844355 _z(OCoLC)970734185 _z(OCoLC)971040738 _z(OCoLC)971088880 _z(OCoLC)973120944 _z(OCoLC)974650732 _z(OCoLC)980215135 _z(OCoLC)980921420 _z(OCoLC)981103453 _z(OCoLC)985038357
040			_aEBLCP _cEBLCP _dOCLCQ _dYDX _dN$T _dGW5XE _dIDEBK _dAZU _dOCLCF _dUAB _dCOO _dUPM _dCNCGM _dIOG _dVT2 _dESU _dJBG _dIAD _dGZM _dICW _dICN _dOH1 _dOCLCQ _dU3W _dES-MaUEC _bspa
050		4	_aTK7888.4 _bC667 2016 EB
245	0	0	_aComputing platforms for software-defined radio _cWaqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia, editors.
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (241 páginas)
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
500			_a6.4.1 WCDMA Cell Search.
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
504			_aIncluye referencias bibliográficas
505	0		_aPreface; Acknowledgements; Contents; Contributors; 1 The Evolution of Software-Defined Radio: An Introduction; Part-I: Architectures, Designs, and Implementations; Part-II: Software-Based Radio Cognition and Implementation Tools; Reference; Part I Architectures, Designs and Implementations; 2 Design Transformation from a Single-Core to a Multi-Core Architecture Targeting Massively Parallel Signal Processing Algorithms; 2.1 Introduction; 2.2 Existing State of the Art; 2.2.1 MORPHEUS; 2.2.2 P2012; 2.2.3 NineSilica; 2.2.4 RAW; 2.2.5 CRISP; 2.2.6 Intel's Single-Chip Cloud Computer; 2.2.7 TILE64™
505	8		_a2.3 Scalable CGRAs2.4 The Network-on-Chip; 2.5 Hardware/Software Integration; 2.5.1 Loading Configuration and Data; 2.5.2 Context Enabling and Execution; 2.5.3 Synchronization; 2.6 Heterogeneous Accelerator-Rich Reconfigurable Platform; 2.7 Application Mapping; 2.8 Measurement and Estimation; 2.9 Evaluation and Comparisons; 2.10 Conclusions; References; 3 The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio; 3.1 Introduction; 3.2 Related Work; 3.3 The CoreVA-MPSoC Architecture; 3.3.1 CoreVA VLIW CPU; 3.3.2 CPU Cluster; 3.3.3 Network-on-Chip; 3.3.3.1 Switch Box.
505	8		_a3.3.3.2 Network Interface3.3.3.3 Globally Asynchronous Locally Synchronous; 3.4 Implementation Results in a 28nm FD-SOI Technology; 3.4.1 CoreVA VLIW CPU Implementation Results; 3.4.2 MPSoC Implementation Results; 3.5 Programming the CoreVA-MPSoC; 3.5.1 Communication Model; 3.5.2 StreamIt Language and Compiler; 3.6 Mapping SDR Algorithms to the CoreVA-MPSoC; 3.6.1 Mapping SDR Algorithms to a Single CPU VLIW Core; 3.6.2 Benchmark Results for CoreVA-MPSoC; 3.7 Summary; References; 4 Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array.
505	8		_a4.1 Introduction4.2 Platform Architecture; 4.3 Design Implementation and Algorithm Mapping; 4.3.1 Time Synchronization; 4.3.2 Frequency Offset Estimation; 4.3.3 Channel Estimation; 4.4 Experimental Results and Conclusion; References; 5 Reconfigurable Multiprocessor Systems-on-Chip; 5.1 Introduction and Motivation; 5.2 Background: Reconfigurable Hardware; 5.3 Dynamic and Partial Reconfiguration; 5.3.1 Benefits of Dynamic and Partial Reconfiguration for Software Defined Radio Applications; 5.4 Reconfigurable Multiprocessor Systems-on-Chip.
505	8		_a5.4.1 rMIMD: Multiprocessors with Reconfigurable Instruction Streams5.4.2 MIrMD: Multiprocessors with Reconfigurable Data Streams; 5.4.3 rMIrMD: Multiprocessors with Reconfigurable Instruction and Reconfigurable Data Streams; 5.4.3.1 RAMPSoC; 5.4.3.2 RAR-MPSoC; 5.5 Conclusion and Outlook; References; 6 Ninesilica: A Homogeneous MPSoC Approach for SDR Platforms; 6.1 Introduction; 6.2 Ninesilica Architecture; 6.2.1 Network-on-Chip; 6.2.2 Power Management; 6.2.3 I/O Management; 6.2.4 Hardware Implementation; 6.3 Cases Studies; 6.3.1 WCDMA; 6.3.2 OFDM; 6.4 Analysis of Results.
520	3		_aThis book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. Coverage includes architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability. Describes a computer engineering approach to SDR baseband processing hardware; Discusses implementation of numerous compute-intensive signal processing algorithms on single and multicore platforms; Enables deep understanding of optimization techniques related to power and energy consumption of multicore platforms using several basic and high-level performance indicators; Includes prototyping details of single and multicore platforms on ASICs and FPGAs.
650		7	_aSoftware _2embne _0(OCoLC)fst01124214 _0 _9143838
700	1		_aGarzia, Fabio.
700	1		_aHussain, Waqar, _eeditor literario
700	1		_aIsoaho, Jouni.
700	1		_aNurmi, Jari.
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-49679-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017B
998			_b02/2018 _dz _e- _zSI
999			_c95177 _d95177 _x1