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001			95157
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006			m d
007			cr |||||||||||
008			170104s2017 sz o 000 0 eng d
020			_a331931596X _q(electronic bk.)
020			_a9783319315966 _q(electronic bk.)
020			_z9783319315942
035			_a(OCoLC)967831906 _z(OCoLC)967655951
040			_aIDEBK _cIDEBK _dEBLCP _dN$T _dGW5XE _dN$T _dYDX _dUAB _dOCLCF _dCOO _dCNCGM _dIOG _dESU _dJBG _dIAD _dICW _dICN _dOTZ _dOCLCQ _dU3W _dES-MaUEC _bspa
050		4	_aTK7874 _b.T443 2017 EB
245	0	4	_aThe dark side of silicon : _benergy efficient computing in the dark silicon era _cAmir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, Hannu Tenhunen, editors.
264		1	_aSwitzerland _bSpringer _c2017
300			_a1 recurso en línea
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
505	0		_aPart I Architecture and Implementation Perspective; 1 A Perspective on Dark Silicon; The Dark Silicon Phenomenon; Power Density; Power Consumption in CMOS Chips; Slack Voltage Scaling; Leakage Power; Thermal Issues; Challenges and Consequences of Dark Silicon; Performance; Energy Efficiency; Resource Allocation and Utilization; Thermal Management; Solutions for Dark Silicon; Architecture and Implementation Perspective; Run-Time Resource Management: Computational Perspective; Design and Management: Communication Perspective; Summary; References
505	8		_a2 Dark vs. Dim Silicon and Near-Threshold ComputingIntroduction; Related Work; Lumos Framework; Technology Modeling; Frequency Modeling; Core Modeling; Power; Performance; Baseline; Accelerator Modeling; Workload Modeling; System Configuration; Discussions; Lumos Release; Design Space Exploration; Effectiveness of Dim Silicon with Near-Threshold Operation; Dim Silicon with Reconfigurable Logic; Dim Silicon with ASICs; Dim Silicon with Accelerators(RL and ASIC) on General-Purpose Workload; Benefit of ASIC Accelerators; Sensitivity of ASIC Performance Ratio; Alternative Serial Cores
505	8		_aConclusionsReferences; 3 The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric; Introduction; State-of-the-Art Review and Problem Analysis; State-of-the-Art Review of the Techniques to Deal with Dark Silicon Constraints; Problem Analysis; Partial Computation-Centric Customization; Inefficient Software-Centric Implementation Style; Lack of Dynamic Runtime Customization; Large Engineering Cost for Customization; The SiLago Platform; Dynamically Reconfigurable Resource Array; Distributed Memory Architecture
505	8		_aDynamic Customization of Parallelism and Voltage Frequency ScalingThe Global Interconnect and Reconfiguration Infrastructure in the SiLago Platform; Flexilators and System Controller; Private Execution Partitions: Complete and Dynamic Hardware Centric Custom Implementation for a Predictable and Composable System; Differentiating SiLago Platform with Other Implementation Styles; Automating the Complete Customization; SiLago Physical Design Platform Overview; SiLago Platform Based Design Flow vs. Standard Cell Based Design Flow; The SiLago Design Flow: Automating the Customization
505	8		_aSiLago Physical Design Platform DevelopmentFunction Implementation Library Using AlgoSil High-Level Synthesis; Sub-System/Application-Level Synthesis Using Sylva; Experimental Results; Computational and Silicon Efficiencies of the SiLago Platform; Complete Customization of the SiLago Platform; Dynamic Parallelism and Voltage Frequency Scaling; SiLago Design Methodology; The Overhead Incurred by SiLago's Application-Level Synthesis; The Efficiency of FIMP Library Development; Conclusion and Future Work; References
520	3		_aThis book presents the state-of-the art of one of the main concerns with microprocessors today, a phenomenon known as "dark silicon". Readers will learn how power constraints (both leakage and dynamic power) limit the extent to which large portions of a chip can be powered up at a given time, i.e. how much actual performance and functionality the microprocessor can provide. The authors describe their research toward the future of microprocessor development in the dark silicon era, covering a variety of important aspects of dark silicon-aware architectures including design, management, reliability, and test. Readers will benefit from specific recommendations for mitigating the dark silicon phenomenon, including energy-efficient, dedicated solutions and technologies to maximize the utilization and reliability of microprocessors. Enables readers to understand the dark silicon phenomenon and why it has emerged, including detailed analysis of its impacts; Presents state-of-the-art research, as well as tools for mitigating the dark silicon phenomenon; Includes coverage of various aspects of dark silicon awareness in design, management, reliability, and tests.
650		7	_aCircuitos integrados _xDesign and construction. _2embne _0(OCoLC)fst00975545 _0 _9139614
700	1		_aHemani, Ahmed.
700	1		_aJantsch, Axel.
700	1		_aLiljeberg, Pasi.
700	1		_aRahmani, Amir M.
700	1		_aTenhunen, Hannu.
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-31596-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017B
998			_b02/2018 _dz _e- _zSI
999			_c95157 _d95157 _x1