000			04910cam a2200457Ii 4500
001			94969
003			ES-MaUEC
005			20230102112640.0
006			m o d
007			cr cnu|||unuuu
008			161202s2017 sz ob 000 0 eng d
020			_a3319488988
020			_a3319488996 _q(electronic bk.)
020			_a9783319488981
020			_a9783319488998 _q(electronic bk.)
020			_z9783319488981 _q(print)
035			_a(OCoLC)964698693 _z(OCoLC)974651743 _z(OCoLC)981099953 _z(OCoLC)1005800132
040			_aN$T _cN$T _dIDEBK _dEBLCP _dGW5XE _dN$T _dIDB _dAZU _dUAB _dCNCGM _dOCLCF _dYDX _dUPM _dIOG _dVT2 _dUWO _dESU _dJBG _dIAD _dICW _dICN _dOTZ _dOCLCQ _dU3W _dES-MaUEC _bspa
050		4	_aTK7868.L6 _bP677 2017 EB
100	1		_aPosser, Gracieli, _eautor
245	1	0	_aElectromigration inside logic cells : _bmodeling, analyzing and mitigating signal electromigration in NanoCMOS _cGracieli Posser, Sachin S. Sapatnekar, Ricardo Reis.
264		1	_aCham, Switzerland _bSpringer _c2017
300			_a1 recurso en línea
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
504			_aIncluye referencias bibliográficas
505	0		_aPreface; Acknowledgments; Contents; List of Figures; List of Tables; Abbreviations; 1 Introduction; 1.1 Reliability and Electromigration; 1.2 Electromigration in Future Technologies; 1.3 Motivation and Contributions; 1.4 Monograph Outline; 2 State of the Art; 2.1 Mitigating the EM Effects in Different IC Design Flow Stages; 2.1.1 Managing Electromigration in Logic Designs; 2.1.2 Electromigration Impact in Future Technologies; 2.1.3 Smart Non-default Routing for Clock Power Reduction; 2.1.4 Impacts of Electromigration Awareness.
505	8		_a2.2 Mitigating the EM Effects in Different Types of Interconnections2.2.1 TSVs; 2.2.2 Power Delivery Network; 2.2.3 Clock Network; 2.2.4 Vias; 2.2.5 Signal Interconnects; 2.2.6 Cell-Internal EM; 2.2.6.1 Accurate Current Estimation for Interconnect Reliability Analysis (Jain12); 2.2.6.2 CMOS Inverter and Standard Cell the Same(patenteempindomae2001cmos); 2.3 Summary of Related Works; 2.4 Conclusions; 3 Modeling Cell-Internal EM; 3.1 Modeling Time-to-Failure Under EM; 3.2 Joule Heating; 3.2.1 Local Hot Spots from Joule Heating; 3.3 Current Divergence.
505	8		_a3.3.1 New Electromigration Validation: Via Node Vector Method3.3.2 Applying Current Divergence in the Proposed EM Model; 3.3.3 The Impact of Blech Length on Cell-Internal Interconnects; 3.4 Conclusions; 4 Current Calculation; 4.1 Current Flows Using Graph Traversals; 4.2 Algebra for Average/RMS Current Updates; 4.2.1 Algebra for Computing Average Current; 4.2.2 Algebra for Computing the RMS Current; 4.2.2.1 Example; 4.3 Results; 5 Experimental Setup; 6 Results; 6.1 The Electromigration Effects for Different Logic Gates; 6.1.1 NAND2_X2 and NOR2_X2 Gates.
505	8		_a6.1.1.1 TTF Improvement by Layout Modifications6.1.2 AOI21_X2; 6.1.2.1 TTF Improvement by Layout Modifications; 6.1.3 NOR2_X4; 6.1.4 INV_X16; 6.2 Conclusion; 7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths; 7.1 Experimental Setup; 7.2 Simulation Results; 7.3 Conclusion; 8 Conclusions; 8.1 Future Works; A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness; B Coupling Capacitance Currents; References.
520	3		_aThis book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.
650		7	_aIones _2embne _0(OCoLC)fst00906436 _0 _9676271
700	1		_aReis, Ricardo _eautor _9100026
700	1		_aSapatnekar, Sachin S., _d1967- _eautor
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-48899-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017B
998			_b02/2018 _dz _e- _zSI
999			_c94969 _d94969 _x1