000			02712cam a2200397Ii 4500
999			_c94749 _d94749 _x1
001			94749
003			ES-MaUEC
005			20230102112630.0
006			m o d
007			cr cnu---unuuu
008			161024s2017 sz o 001 0 eng d
020			_a3319424386 _q(electronic bk.)
020			_a9783319424385 _q(electronic bk.)
020			_z3319424378
020			_z9783319424378
035			_a(OCoLC)961116899 _z(OCoLC)961207311 _z(OCoLC)964568453
040			_aN$T _cN$T _dN$T _dYDX _dIDEBK _dGW5XE _dCOO _dUAB _dIOG _dESU _dZ5A _dJBG _dIAD _dICW _dICN _dOTZ _dOCLCQ _dCNCGM _dU3W _dES-MaUEC _bspa
050		4	_aTK7895.G36 _bD475 2017 EB
245	0	0	_aDesigning with Xilinx FPGAs : _busing Vivado _cSanjay Churiwala, editor
264		1	_aSwitzerland _bSpringer _c[2017]
300			_a1 recurso en línea (x, 260 páginas)
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
500			_aSpringerLink
504			_aIncluye referencias bibliográficas
505	0		_aState of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
520	3		_aThis book helps readers to implement their designs on Xilinx® FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado® Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.
588	0		_aVersión impresa
988			_aEBOOK, EBSPRINGER_2017A
650		7	_2embne _aDispositivos FPGAs _9667973
700	1		_aChuriwala, Sanjay, _eeditor literario
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-42438-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2018 _dz _e- _zSI