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001			94472
003			ES-MaUEC
005			20230102112614.0
006			m o d
007			cr cnu---unuuu
008			160806t20162017sz o 000 0 eng d
020			_a3319396242 _q(electronic bk.)
020			_a9783319396248 _q(electronic bk.)
020			_z9783319396231 _q(print)
035			_a(OCoLC)956278088 _z(OCoLC)958350193 _z(OCoLC)960091356
040			_aEBLCP _cEBLCP _dN$T _dYDXCP _dGW5XE _dIDEBK _dOCLCF _dYDX _dOCLCQ _dAZU _dIDB _dIOG _dUAB _dMERER _dESU _dOCLCQ _dJBG _dIAD _dICN _dOTZ _dOCLCQ _dU3W _dMERUC _dES-MaUEC _bspa
050		4	_aTK7887.6 _bR338 2016 EB
100	1		_aRabuske, Taimur.
245	1	0	_aCharge-Sharing SAR ADCs for Low-Voltage Low-Power Applications _cTaimur Rabuske, Jorge Fernandes.
264		1	_aCham _bSpringer
300			_a1 recurso en línea (173 páginas)
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
490	0		_aAnalog Circuits and Signal Processing
500			_aAppendix: Frequency-Dependency of C(V) in MOSCAPs.
500			_aSpringerLink _bSpringer Engineering eBooks 2017 English+International
505	0		_aPreface; Contents; 1 Introduction ; Contents; 1.1 Background; 1.2 Research Goals; 1.3 Book Outline; 1.4 Original Contributions; 1.5 Final Remarks; References; 2 ADCs for Low-Voltage Low-Power Applications ; Contents; 2.1 Introduction; 2.2 Sampling and Quantization; 2.3 Search Methods for Nyquist ADCs; 2.3.1 Direct Search (Flash ADCs); 2.3.2 Binary Search (SAR ADCs); 2.3.3 Pipelined Binary Search (Pipeline ADCs); 2.3.4 Summary; 2.4 The SAR ADC; References; 3 Review of SAR ADC Switching Schemes ; Contents; 3.1 Introduction; 3.2 Operation Modes of Charge-Based SAR ADCs.
505	8		_a3.2.1 The Charge Redistribution Principle3.2.2 The Charge Sharing Principle; 3.3 Charge Redistribution Switching Schemes; 3.3.1 Conventional Switching; 3.3.2 Monotonic or "Set-and-Down'' Switching; 3.3.3 vcm-Based Capacitor Switching; 3.3.4 Tri-Level Capacitor Switching; 3.4 Charge Sharing Switching Scheme; 3.5 Comparison of Reviewed Switching Schemes; 3.6 State of the Art in CS-ADCs; 3.6.1 Craninckx and van der Plas ch3:Craninckx2007; 3.6.2 Giannini et al. ch3:Giannini2008; 3.6.3 Tsai et al. ch3:Tsai2011; 3.6.4 Malki et al. ch3:Malki2012,ch3:Malki2014; 3.6.5 Summary.
505	8		_a4.6.1 Differential Nonlinearity4.6.2 Integral Nonlinearity; 4.6.3 ENOB; 4.6.4 Model Verification; 4.6.5 Discussion; 4.7 Errors Caused by Noise; References; 5 Noise-Aware Synthesis and Optimization of Voltage Comparators ; Contents; 5.1 Introduction; 5.2 Review on Comparator Noise Calculation; 5.3 Comparator Noise Measurement; 5.4 Multi-Objective Optimization Framework; 5.5 Design Example; 5.6 Results; 5.7 Discussion; References; 6 An 8-Bit 0.35-V CS-ADC with Comparator Offset Auto-Zero and Voltage Boosting; Contents; 6.1 Introduction; 6.2 CS-ADC with Background Comparator Offset Auto-Zeroing.
505	8		_a6.2.1 Operation Principle of the Proposed CS-ADC6.2.2 Background Comparator Offset Self-Zeroing; 6.3 SAR ADC Implementation; 6.3.1 Self-Calibrated Comparator; 6.3.2 Local Voltage Boosting; 6.3.3 Full-Custom Self-Timed SAR Controller; 6.3.4 TH and DAC; 6.4 Experimental Results; 6.5 Discussion; References; 7 A 9-Bit 0.6-V CS-ADC with a MOSCAP-DAC; Contents; 7.1 Introduction; 7.2 CS-ADC with a MOSCAP-Based DAC; 7.3 SAR ADC Implementation; 7.3.1 Comparator; 7.3.2 Configurable TH with Boost-and-Bootstrap Switches; 7.3.3 Voltage Boosters; 7.3.4 DAC Cells; 7.4 Experimental Results; 7.5 Discussion.
505	8		_aAppendix: Voltage and Energy in CR ADCsModels for Voltage and Energy in CR ADCs; Simplified Voltage Model for CR DACs; General Voltage Model for CR DACs; Codes; References; 4 Effects of Nonidealities on the Performance of CS-ADCs ; Contents; 4.1 Introduction; 4.2 Trajectory of the DAC Voltage in a CS-ADC; 4.3 Analog-to-Digital Conversion Gain; 4.4 Errors Caused by Mismatch; 4.4.1 Mismatch Between TH Capacitors; 4.4.2 Mismatch Between TH and Total DAC Capacitance; 4.4.3 Mismatch Between DAC Capacitors; 4.5 Errors Caused by Parasitics; 4.6 Errors Caused by Comparator Offset.
520	3		_aThis book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
650		7	_aConvertidores analógicos-digitales _2embne _0(OCoLC)fst01895552 _0 _9667192
700	1		_aFernandes, Jorge.
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=http://link.springer.com/10.1007/978-3-319-39624-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
988			_aEBOOK, asignarmaterias, EBSPRINGER_2017A
998			_b02/2018 _dz _e- _zSI
999			_c94472 _d94472 _x1