000			03811nam a22003855i 4500
001			88402
003			ES-MaUEC
005			20230207040632.0
007			cr nn 008mamaa
008			161130s2016 xxu| s |||| 0|eng d
020			_a9781489977977
024	7		_a10.1007/978-1-4899-7797-7 _2doi
040			_aES-MaUEC
050		4	_aQA76.58 _b.A35 2016 EB
100	1		_aAiken, Alex _9102045 _0Local
245	1	0	_aInstruction Level Parallelism _cby Alex Aiken, Utpal Banerjee, Arun Kejariwal, Alexandru Nicolau
260			_aBoston, MA _bSpringer _c2016
300			_a1 recurso en línea (XXI, 255 p.) _b78 ilustraciones, 30 ilustraciones en color
336			_aTexto (visual) _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
505	0		_aIntroduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue.
520			_aSince its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
942			_2lcc _cLE
988			_aEBOOK, EBSPRINGER
650		7	_aProceso paralelo (Informática) _0comprobar BNE20012044022 _2embne _9158747
700	1		_aBanerjee, Utpal _9102046 _0Local
700	1		_aKejariwal, Arun _9102047 _0Local
700	1		_aNicolau, Alexandru _9102048 _0Local
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-1-4899-7797-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9781489977977
907			_a.b12984097 _b10-10-17 _c22-03-17
998			_am _a_alco _a_vill _b21-03-17 _cm _dz _ea _feng _gxxu _h0
945			_aQA76.58 .A35 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i11605133 _z06-04-17
999			_c88402 _d88402 _x1