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| 008 | 160517s2016 ii | s |||| 0|eng d | ||
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_aTK7868.L6 _bT37 2016 EB |
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| 082 | 0 | 4 | _a621.3815 |
| 100 | 1 |
_aTaraate, Vaibbhav _0Local _9100582 |
|
| 245 | 1 | 0 |
_aDigital logic design using verilog : _bcoding and RTL synthesis _cby Vaibbhav Taraate |
| 260 |
_aNew Delhi _bSpringer _c2016 |
||
| 300 |
_a1 recurso en línea (XXIII, 416 p.) _b267 ilustraciones, 226 ilustraciones en color |
||
| 336 |
_aTexto (visual) _btxt _2rdacontent |
||
| 337 |
_aelectrónico _bc _2rdamedia |
||
| 338 |
_arecurso electrónico _bcr _2rdacarrier |
||
| 505 | 0 | _aIntroduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs | |
| 520 | _aThis book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists | ||
| 650 | 7 |
_aCircuitos lógicos _0comprobar BNE19900968733 _2embne _9139135 |
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| 710 | 2 |
_aSpringerLink (Online service) _0Local _9106996 |
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_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-81-322-2791-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 901 | _ai9788132227915 | ||
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_a.b12959613 _b10-10-17 _c21-11-16 |
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