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008			150706s2016 ii | s |||| 0|eng d
020			_a9788132225201
040			_aES-MaUEC
050		4	_aTK7895.G36 _bP353 2016
082	0	4	_a621.3815
100	1		_aPalchaudhuri, Ayan. _9100494 _0Local
245	1	0	_aHigh Performance Integer Arithmetic Circuit Design on FPGA : _bArchitecture, Implementation and Design Automation _cby Ayan Palchaudhuri, Rajat Subhra Chakraborty
260			_aNew Delhi _bSpringer India _c2016
300			_a1 recurso en línea (XVII, 114 páginas) _b56 ilustraciones
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
490	0		_aSpringer Series in Advanced Microelectronics _x1437-0387 _v51
505	0		_aIntroduction -- Architecture of Target FPGA Platform -- A Fabric Component based Design Approach for High Performance Integer Arithmetic Circuits -- Architecture of Data path Circuits -- Architecture of Control path Circuits -- Compact FPGA Implementation of Linear Cellular Automata -- Design Automation and Case Studies -- Conclusions and Future Work.
520	3		_aThis book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary zUser Constraints Filey. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation.
650	0	7	_aComponentes electrónicos _9153705 _2embne
650		7	_aElectrónica _0comprobar BNE19900963053 _2embne _9138690
700	1		_aChakraborty, Rajat Subhra _0Local _9100495
710	2		_aSpringerLink (Online service) _0Local _9106996
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-81-322-2520-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9788132225201
907			_a.b12959091 _b10-10-17 _c21-11-16
942			_2lcc _cLE
945			_aTK7895.G36 P353 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i1160055x _z06-04-17
988			_aEBOOK, asignarmaterias , EBSPRINGER
998			_am _a_alco _a_vill _b - - _cm _dz _e- _feng _gii _h0