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008			150805s2016 ii | s |||| 0|eng d
020			_a9788132225089
040			_aES-MaUEC
050		4	_aTK7871.95 _bF863 2016 EB
082	0	4	_a621.3815
245	1	0	_aFundamentals of Bias Temperature Instability in MOS Transistors : _bCharacterization Methods, Process and Materials Impact, DC and AC Modeling _cedited by Souvik Mahapatra
250			_a1st ed. 2015.
260			_aNew Delhi _bSpringer India _c2016
300			_a1 recurso en línea (XVI, 269 p.) _b201 ilustraciones, 67 ilustraciones en color
336			_aTexto (visual) _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
490	1		_aSpringer Series in Advanced Microelectronics _x1437-0387 _v52
505	0		_aIntroduction: Bias Temperature Instability (BTI) in N and P Channel MOSFETs -- Characterization Methods for BTI Degradation and Associated Gate Insulator Defects -- Physical Mechanism of BTI Degradation Direct Estimation of Trap Generation and Trapping -- Physical Mechanism of BTI Degradation Modeling of Process and Material Dependence -- Reaction-Diffusion Model -- Modeling of DC and AC NBTI Degradation and Recovery for SiON and HKMG MOSFETs -- Index.
520			_aThis book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life, and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also in Si FinFETs. The contents also include a detailed investigation of the gate insulator process dependence of BTI in differently processed SiON and HKMG MOSFETs. The book then goes on to discuss Reaction-Diffusion (RD) model to estimate generation of new traps for DC and AC NBTI stress, and Transient Trap Occupancy Model (TTOM) to estimate charge occupancy of generated traps and their contribution to BTI degradation. Finally, a comprehensive NBTI modeling framework including TTOM enabled RD model and hole trapping to predict time evolution of BTI degradation and recovery during and after DC stress for different stress and recovery biases and temperature, during consecutive arbitrary stress and recovery cycles, and during AC stress at different frequency and duty cycle. The contents of this book should prove useful to academia and professionals alike.
710	2		_aSpringerLink (Online service) _0Local _9106996
942			_2lcc _cLE
988	0	0	_aEBOOK, EBSPRINGER
650		7	_aFísica del estado sólido _0comprobar BNE19900958620 _2embne _9405016
650		7	_aElectrónica _0comprobar BNE19900963053 _2embne _9138690
650	0	7	_aIngeniería _vCongresos y asambleas _0LocalX _2embne _9670301
700	1		_aMahapatra, Souvik. _eeditor literario _9100491 _0Local
830		0	_aSpringer Series in Advanced Microelectronics _x1437-0387 _v52 _9134193
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-81-322-2508-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9788132225089
907			_a.b12959078 _b10-10-17 _c21-11-16
998			_am _a_alco _a_vill _b - - _cm _dz _e- _feng _gii _h0
945			_aTK7871.95 F863 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i11600548 _z06-04-17
999			_c86629 _d86629 _x1