000			03440nam a22004095i 4500
001			85949
003			ES-MaUEC
005			20230207040535.0
007			cr nn 008mamaa
008			160621s2016 gw a s 000 0 eng d
020			_a9783319327594
024	7		_a10.1007/978-3-319-32759-4 _2doi
040			_aES-MaUEC
050		4	_aTK7888.4 _b.S65 2016 EB
082	0	4	_a621.3815
100	1		_aSpiridon, Silvian _999292 _0Local
245	1	0	_aToward 5G Software Defined Radio Receiver Front-Ends _cby Silvian Spiridon
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (XVII, 96 p.) _b50 ilustraciones, 20 ilustraciones en color
336			_aTexto (visual) _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
490	1		_aSpringerBriefs in Electrical and Computer Engineering _x2191-8112
505	0		_aOverview of Wireless Communication in the Internet Age -- Defining the optimal architecture -- From High Level Standard Requirements to Circuit Level Electrical Specifications: A Standard Independent Approach -- Optimal Filter Partitioning -- Smart Gain Partitioning for Noise Linearity Trade-Off Optimization -- SDRX Electrical Specifications -- A System Level Perspective of Modern Receiver Building Blocks -- Conclusions and Future Developers.
520			_aThis book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion architecture. This allows readers give a power consumption budget to determine how much filtering is required on the receive path, by considering the ADC performance characteristics and the corresponding blocker diagram.
710	2		_aSpringerLink (Online service) _0Local _9106996
942			_2lcc _cLE
988			_aEBOOK, EBSPRINGER
650		7	_aCircuitos lógicos _0comprobar BNE19900968733 _2embne _9139135
650		7	_9138689 _aMicroelectrónica _0comprobar BNE19900963042 _2embne
830		0	_aSpringerBriefs in Electrical and Computer Engineering _x2191-8112 _9134065
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-3-319-32759-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9783319327594
907			_a.b12952278 _b10-10-17 _c21-11-16
998			_am _a_alco _a_vill _b21-09-17 _cm _dz _ei _feng _ggw _h0
945			_aTK7888.4 .S65 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i11594986 _z06-04-17
999			_c85949 _d85949 _x1