000			03134nam a22003975i 4500
001			85743
003			ES-MaUEC
005			20230207040525.0
007			cr nn 008mamaa
008			160225s2016 gw a s 001 0 eng d
020			_a9783319306070
024	7		_a10.1007/978-3-319-30607-0 _2doi
040			_aES-MaUEC
050		4	_aTK5102.96 _b.S29 2016 EB
082	0	4	_a621.3815
100	1		_aSayil, Selahattin _998922 _0Local
245	1	0	_aSoft Error Mechanisms, Modeling and Mitigation _cby Selahattin Sayil
250			_a1st ed.
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (XI, 105 p.) _b81 ilustraciones, 35 ilustraciones en color
336			_aTexto (visual) _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
505	0		_aIntroduction -- Mitigation of Single Event Effects -- Transmission Gate (TG) Based Soft Error Mitigation Methods -- Single Event Soft Error Mechanisms -- Modeling Single Event Crosstalk Noise in Nanometer Technologies -- Modeling of Single Event Coupling Delay and Speedup Effects -- Single Event Upset Hardening of Interconnects -- Soft-Error Aware Power Optimization -- Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation.
520			_aThis book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time.
710	2		_aSpringerLink (Online service) _0Local _9106996
942			_2lcc _cLE
988			_aEBOOK, EBSPRINGER
650		7	_aInformación, Teoría de la _0comprobar BNE19900986687 _2embne _9140554
650		7	_9139610 _aCircuitos electrónicos _0comprobar BNE19900974538 _2embne
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-3-319-30607-0 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9783319306070
907			_a.b1295021x _b10-10-17 _c21-11-16
998			_am _a_alco _a_vill _b23-09-17 _cm _dz _eo _feng _ggw _h0
945			_aTK5102.96 .S29 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i11593337 _z06-04-17
999			_c85743 _d85743 _x1