000			03418nam a22003855i 4500
710	2		_aSpringerLink (Online service) _0Local _9106996
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008			150827s2016 gw | s |||| 0|eng d
020			_a9783319220352
040			_aES-MaUEC
050		4	_aTK7874.75 _bM643 2016
082	0	4	_a621.3815
100	1		_997289 _aMohamed, Khaled Salah _0Local
245	1	0	_aIP Cores Design from Specifications to Production : _bModeling, Verification, Optimization, and Protection _cby Khaled Salah Mohamed
260			_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (IX, 154 páginas) _b153 ilustraciones, 115 ilustraciones en color
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
490	0		_aAnalog Circuits and Signal Processing _x1872-082X
505	0		_a1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
520	3		_aThis book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including� those associated with many of the most common memory cores, controller IPs� and system-on-chip (SoC) buses. Readers will also benefit from the author�s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.� A SoC case study is presented to compare traditional verification with the new verification methodologies. ·�������� Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; ·�������� Introduce a deep introduction for Verilog for both implementation and verification point of view.� ·�������� Demonstrates how to use IP in applications such as memory controllers and SoC buses. ·�������� Describes a new verification methodology called bug localization; ·�������� Presents a novel scan-chain methodology for RTL debugging; ·�������� Enables readers to employ UVM methodology in straightforward, practical terms.
650		7	_aMicroprocesadores _9141164 _0comprobar BNE19900994978 _2embne
650		7	_aElectrónica _0comprobar BNE19900963053 _2embne _9138690
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://link.springer.com/book/10.1007/978-3-319-22035-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
901			_ai9783319220352
907			_a.b12940872 _b10-10-17 _c21-11-16
942			_2lcc _cLE
945			_aTK7874.75 M643 2016 EB _g1 _ieBOOK _j0 _lmae _o- _pEUR0.00 _q- _r- _sb _t15 _u0 _v0 _w0 _x0 _y.i11585286 _z06-04-17
988			_aEBOOK, asignarmaterias , EBSPRINGER
998			_am _a_alco _a_vill _b - - _cm _dz _e- _feng _ggw _h0