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008			230125s2023 sz | o |||| 0|eng d
020			_a9783031180231
024	7		_a10.1007/978-3-031-18023-1 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9 .A73 _b2023 EB
100	1		_aGoossens, Bernard _eautor _4http://id.loc.gov/vocabulary/relators/aut _9689671
245	1	0	_aGuide to Computer Processor Architecture : _bA RISC-V Approach, with High-Level Synthesis _cby Bernard Goossens
250			_a1st ed 2023
264		1	_aCham _bSpringer International Publishing _c2023
300			_a1 recurso en línea
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	0		_aUndergraduate Topics in Computer Science _x2197-1781
505	0		_aPart I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores.
520			_aThis unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.
988			_aSpringer_Computer_2023
650		7	_2embne _9144554 _aArquitectura de ordenador
650		7	_2embne _9141164 _aMicroprocesadores
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-18023-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2024 _dz _eIG _zSI