000			03685nam a2200397 i 4500
999			_c398042 _d398042 _x1
001			398042
003			ES-MaUEC
005			20240314174517.0
006			a|||||o|||| 00| 0
007			cr nn 008mamaa
008			230301s2023 si | o |||| 0|eng d
020			_a9789811985515
024	7		_a10.1007/978-981-19-8551-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874 _b2023 EB
100	1		_aLi, Xiaowei _d1964- _eautor _0(orcid)0000-0002-0874-814X _1https://orcid.org/0000-0002-0874-814X _4http://id.loc.gov/vocabulary/relators/aut _9689506
245	1	0	_aBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design : _bA Self-Test, Self-Diagnosis, and Self-Repair-Based Approach _cby Xiaowei Li, Guihai Yan, Cheng Liu
250			_a1st ed 2023
264		1	_aSingapore _bSpringer Nature _c2023
300			_a1 recurso en línea
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aChapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion.
520			_aWith the end of Dennard scaling and Moore's law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or "3S" for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. .
988			_aSpringer_Computer_2023
650		7	_2embne _9139614 _aCircuitos integrados
700	1		_9689507 _aYan, Guihai _eautor
700	1		_912362 _aLiu, Cheng _eautor
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-19-8551-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2024 _dz _eb _zSI