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020			_a9789811661204
024	7		_a10.1007/978-981-16-6120-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7871.99.M44 _b2022 EB
245	0	0	_aRecent Advances in PMOS Negative Bias Temperature Instability : _bCharacterization and Modeling of Device Architecture, Material and Process Impact _cedited by Souvik Mahapatra
250			_a1st edition 2022
264		1	_aSingapore _bSpringer International Publishing _c2022
300			_a1 recurso en línea (XXIII, 311 páginas) _b213 ilustraciones, 189 ilustraciones a color
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
505	0		_aCharacterization of NBTI Parametric Drift -- BAT Framework Modeling of Gate First HKMG Si and SiGe Channel FDSOI MOSFETs -- BTI Analysis Tool (BAT) Model Framework -- BAT Framework Modeling of RMG HKMG SOI FinFETs -- BAT Framework Modeling of RMG HKMG GAA-SNS FETs -- BAT Framework Modeling of RMG HKMG Si and SiGe Channel FinFETs -- BAT Framework Modeling of Gate First HKMG Si Channel MOSFETs -- BAT Framework Modeling of AC NBTI: Stress Mode, Duty Cycle and Frequency -- BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs -- BTI Analysis Tool (BAT) Model Framework - Generation of Interface Traps -- Device Architecture, Material and Process Dependencies of NBTI Parametric Drift -- Physical Mechanism of NBTI Parametric Drift -- BAT Framework Modeling of Gate First HKMG Si-capped SiGe Channel MOSFETs -- BTI Analysis Tool (BAT) Model Framework - Interface Trap Occupancy and Hole Trapping.
520			_aThis book covers advances in Negative Bias Temperature Instability (NBTI) and will prove useful to researchers and professionals in the semiconductor devices areas. NBTI continues to remain as an important reliability issue for CMOS transistors and circuits. Development of NBTI resilient technology relies on utilizing suitable stress conditions, artifact free measurements and accurate physics-based models for the reliable determination of degradation at end-of-life, as well as understanding the process, material and device architectural impacts. This book discusses: Ultra-fast measurements and modelling of parametric drift due to NBTI in different transistor architectures: planar bulk and FDSOI p-MOSFETs, p-FinFETs and GAA-SNS p-FETs, with Silicon and Silicon Germanium channels. BTI Analysis Tool (BAT), a comprehensive physics-based framework, to model the measured time kinetics of parametric drift during and after DC and AC stress, at different stress and recovery biases and temperature, as well as pulse duty cycle and frequency. The Reaction Diffusion (RD) model is used for generated interface traps, Transient Trap Occupancy Model (TTOM) for charge occupancy of the generated interface traps and their contribution, Activated Barrier Double Well Thermionic (ABDWT) model for hole trapping in pre-existing bulk gate insulator traps, and Reaction Diffusion Drift (RDD) model for bulk trap generation in the BAT framework; NBTI parametric drift is due to uncorrelated contributions from the trap generation (interface, bulk) and trapping processes. Analysis and modelling of Nitrogen incorporation into the gate insulator, Germanium incorporation into the channel, and mechanical stress effects due to changes in the transistor layout or device dimensions; similarities and differences of (100) surface dominated planar and GAA MOSFETs and (110) sidewall dominated FinFETs are analysed.
988			_aSpringer_Engineering_2022
650		7	_2embne _9140004 _aSemiconductores
650		7	_2embne _9160755 _aCircuitos integrados CMOS
776	0	8	_iPrinted edition: _z9789811661198
776	0	8	_iPrinted edition: _z9789811661211
776	0	8	_iPrinted edition: _z9789811661228
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi-org.ezproxy.universidadeuropea.es/10.1007/978-981-16-6120-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2023 _dz _eIG _zSI