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| 999 |
_c395516 _d395516 |
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| 001 | 395516 | ||
| 003 | ES-MaUEC | ||
| 005 | 20230410101735.0 | ||
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| 007 | cr nn 008mamaa | ||
| 008 | 211031s2022 si | s |||| 0|eng d | ||
| 020 | _a9789811631993 | ||
| 024 | 7 |
_a10.1007/978-981-16-3199-3 _2doi |
|
| 040 |
_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC |
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| 050 | 4 |
_aTK7868 .L6 _b2022 EB |
|
| 100 | 1 |
_aTaraate, Vaibbhav _eautor _9100582 |
|
| 245 | 1 | 0 |
_aDigital Logic Design Using Verilog : _bCoding and RTL Synthesis _cby Vaibbhav Taraate |
| 250 | _a2nd edition 2022 | ||
| 264 | 1 |
_aSingapore _bSpringer International Publishing _c2022 |
|
| 300 |
_a1 recurso en línea (XXV, 604 páginas) _b652 ilustraciones, 529 ilustraciones a color |
||
| 336 |
_atexto _btxt _2rdacontent |
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| 337 |
_aelectrónico _bc _2rdamedia |
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| 338 |
_arecurso electrónico _bcr _2rdacarrier |
||
| 347 |
_aarchivo de texto _bPDF |
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| 505 | 0 | _aIntroduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs. | |
| 520 | _aThis second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. . | ||
| 988 | _aSpringer_Engineering_2022 | ||
| 650 | 7 |
_2embne _9139135 _aCircuitos lógicos |
|
| 776 | 0 | 8 |
_iPrinted edition: _z9789811631986 |
| 776 | 0 | 8 |
_iPrinted edition: _z9789811632006 |
| 776 | 0 | 8 |
_iPrinted edition: _z9789811632013 |
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-16-3199-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
_2lcc _cLE |
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| 998 |
_b03/2023 _dz _eu _zSI |
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