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001			395248
003			ES-MaUEC
005			20230110120135.0
007			cr nn 008mamaa
008			210802s2022 sz | s |||| 0|eng d
020			_a9783030797744
024	7		_a10.1007/978-3-030-79774-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC
050		4	_aQA76.9.A3 _b2022 EB
100	1		_aWijtvliet, Mark. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aBlocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures _cby Mark Wijtvliet, Henk Corporaal, Akash Kumar.
250			_a1st edition 2022
264		1	_aCham _bSpringer International Publishing _c2022
300			_a1 recurso en línea (X, 220 páginas) _b158 ilustraciones, 117 ilustraciones a color
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
505	0		_aIntroduction -- CGRA background -- Concept of the Blocks architecture -- The Blocks framework -- Energy, area, and performance evaluation -- Architectural model -- Case study: the BrainSense platform -- Conclusion.
520			_aThis book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.
776	0	8	_iPrinted edition: _z9783030797737
776	0	8	_iPrinted edition: _z9783030797751
776	0	8	_iPrinted edition: _z9783030797768
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-79774-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aSpringer_Engineering_2022
999			_c395248 _d395248