000			03019nam a22003615i 4500
001			394373
003			ES-MaUEC
005			20230102123124.0
007			cr nn 008mamaa
008			221108s2022 sz | s |||| 0|eng d
020			_a9783031183973
024	7		_a10.1007/978-3-031-18397-3 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC
100	1		_aSrivastava, Pallavi _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aCompletion Detection in Asynchronous Circuits _bToward Solution of Clock-Related Design Challenges _cby Pallavi Srivastava
250			_a1st edition 2022
264		1	_aCham _bSpringer International Publishing _c2022
300			_a1 recurso en línea (XV, 119 páginas) _b65 ilustraciones, 51 ilustraciones a color
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
505	0		_aIntroduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations.
520			_aThis book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.
776	0	8	_iPrinted edition: _z9783031183966
776	0	8	_iPrinted edition: _z9783031183980
776	0	8	_iPrinted edition: _z9783031183997
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-18397-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aSpringer_Computer_2022
999			_c394373 _d394373