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007			cr nn 008mamaa
008			220601s2009 sz | o |||| 0|eng d
020			_a9783031798009
024	7		_a10.1007/978-3-031-79800-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7867 _b2009 EB
100	1		_aSmith, Scott C. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688386
245	1	0	_aDesigning Asynchronous Circuits using NULL Convention Logic (NCL) _cby Scott Smith, Jia Di
250			_a1st edition 2009
264		1	_aCham _bSpringer International Publishing _c2009
300			_a1 recurso en línea (X, 86 páginas)
336			_aTexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Digital Circuits & Systems _x1932-3174
505	0		_aIntroduction to Asynchronous Logic -- Overview of NULL Convention Logic (NCL) -- Combinational NCL Circuit Design -- Sequential NCL Circuit Design -- NCL Throughput Optimization -- Low-Power NCL Design -- Comprehensive NCL Design Example.
520			_aDesigning Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example.
988			_aSynthesis Collection of Technology_2009
650		7	_2embne _9139610 _aCircuitos electrónicos
650		7	_2embne _9139136 _aLógica matemática
700	1		_aDi, Jia _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688387
776	0	8	_iPrinted edition: _z9783031797996
776	0	8	_iPrinted edition: _z9783031798016
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79800-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2023 _dz _eb _zSI