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007			cr nn 008mamaa
008			230509s2010 sz | o |||| 0|eng d
020			_a9783031017285
024	7		_a10.1007/978-3-031-01728-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.545 _b2010 EB
100	1		_aHarris, Tim, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688443 _d1976-
245	1	0	_aTransactional Memory, Second Edition _cby Tim Harris, James Larus, Ravi Rajwar
250			_a1st edition 2010
264		1	_aCham _bSpringer International Publishing _c2010
300			_a1 recurso en línea (XV, 247 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aIntroduction -- Basic Transactions -- Building on Basic Transactions -- Software Transactional Memory -- Hardware-Supported Transactional Memory -- Conclusions.
520			_aThe advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions.
988			_aSynthesis Collection of Technology_2010
650		7	_2embne _9141180 _aProceso de datos
650		7	_2embne _9159594 _aProgramación en paralelo
700	1		_aLarus, James R. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _931261
700	1		_aRajwar, Ravi _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688444
776	0	8	_iPrinted edition: _z9783031006005
776	0	8	_iPrinted edition: _z9783031028564
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01728-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2023 _dz _eIG _zSI