000			03255nam a22004095i 4500
999			_c387875 _d387875
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003			ES-MaUEC
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007			cr nn 008mamaa
008			230427s2016 sz | s |||| 0|eng d
020			_a9783031020315
024	7		_a10.1007/978-3-031-02031-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7871.95 _b2016 EB
100	1		_aGimenez, Salvador Pinillos, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688276 _d1962-
245	1	0	_aLayout Techniques in MOSFETs _cby Salvador Pinillos Gimenez
250			_a1st edition 2016
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (XI, 69 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Emerging Engineering Technologies _x2381-1439
505	0		_aDedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (".
520			_aThis book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
988			_aSynthesis Collection of Technology_2016
650		7	_2embne _9140004 _aSemiconductores
650		7	_2embne _9139614 _aCircuitos integrados
776	0	8	_iPrinted edition: _z9783031009037
776	0	8	_iPrinted edition: _z9783031031595
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-02031-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _eIG _zSI