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008			230427s2016 sz | s |||| 0|eng d
020			_a9783031020278
024	7		_a10.1007/978-3-031-02027-8 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874.75 _b2016 EB
100	1		_aAshraf, Nabil Shovon, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687308 _d1974-
245	1	0	_aNew Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation _cby Nabil Shovon Ashraf, Shawon Alam, Mohaiminul Alam
250			_a1st edition 2016
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (VIII, 72 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Emerging Engineering Technologies _x2381-1439
505	0		_aReview of Research on Scaled Device Architectures and Importance of Lower Substrate Temperature Operation of n-MOSFETs -- Review of Research on Scaled Device Architectures and Importance of Lower Substrate Temperature Operation of n-MOSFETs -- Step-by-Step Computation of Threshold Voltage as a Function of Substrate Temperatures -- Step-by-Step Computation of Threshold Voltage as a Function of Substrate Temperatures -- Simulation Outcomes For Profile of Threshold Voltage As a Function of Substrate Temperature Based on Key Device-Centric Parameters -- Simulation Outcomes For Profile of Threshold Voltage As a Function of Substrate Temperature Based on Key Device-Centric Parameters -- Scaling Projection of Long Channel Threshold Voltage Variability with Substrate Temperatures to Scaled Node -- Scaling Projection of Long Channel Threshold Voltage Variability with Substrate Temperatures to Scaled Node -- Advantage of Lower Substrate Temperature MOSFET Operation to Minimize Short Channel Effects and Enhance Reliability -- Advantage of Lower Substrate Temperature MOSFET Operation to Minimize Short Channel Effects and Enhance Reliability -- A Prospective Outlook on Implementation Methodology of Regulating Substrate Temperatures on Silicon Die -- A Prospective Outlook on Implementation Methodology of Regulating Substrate Temperatures on Silicon Die -- Summary of Research Results -- Conclusion -- References -- Authors' Biographies.
520			_aIn order to sustain Moore's Law-based device scaling, principal attention has focused on toward device architectural innovations for improved device performance as per ITRS projections for technology nodes up to 10 nm. Efficient integration of lower substrate temperatures (.
988			_aSynthesis Collection of Technology_2016
650		7	_2embne _9139614 _aCircuitos integrados
650		7	_2embne _9140004 _aSemiconductores
650		7	_2embne _9167668 _aIngeniería de ordenadores
700	1		_aAlam, Shawon _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688274
700	1		_aAlam, Mohaiminul _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688275
776	0	8	_iPrinted edition: _z9783031008993
776	0	8	_iPrinted edition: _z9783031031557
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-02027-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _eIG _zSI