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007			cr nn 008mamaa
008			230425s2015 sz | s |||| 0|eng d
020			_a9783031017469
024	7		_a10.1007/978-3-031-01746-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.A73 _b2015 EB
100	1		_aHughes, Christopher Justin, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688228 _d1976-
245	1	0	_aSingle-Instruction Multiple-Data Execution _cby Christopher J. Hughes
250			_a1st edition 2015
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XVI, 105 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aPreface -- Acknowledgments -- Data Parallelism -- Exploiting Data Parallelism with SIMD Execution -- Computation and Control Flow -- Memory Operations -- Horizontal Operations -- Conclusions -- Bibliography -- Author's Biography .
520			_aHaving hit power limitations to even more aggressive out-of-order execution in processor cores, many architects in the past decade have turned to single-instruction-multiple-data (SIMD) execution to increase single-threaded performance. SIMD execution, or having a single instruction drive execution of an identical operation on multiple data items, was already well established as a technique to efficiently exploit data parallelism. Furthermore, support for it was already included in many commodity processors. However, in the past decade, SIMD execution has seen a dramatic increase in the set of applications using it, which has motivated big improvements in hardware support in mainstream microprocessors. The easiest way to provide a big performance boost to SIMD hardware is to make it wider-i.e., increase the number of data items hardware operates on simultaneously. Indeed, microprocessor vendors have done this. However, as we exploit more data parallelism in applications, certain challenges can negatively impact performance. In particular, conditional execution, non-contiguous memory accesses, and the presence of some dependences across data items are key roadblocks to achieving peak performance with SIMD execution. This book first describes data parallelism, and why it is so common in popular applications. We then describe SIMD execution, and explain where its performance and energy benefits come from compared to other techniques to exploit parallelism. Finally, we describe SIMD hardware support in current commodity microprocessors. This includes both expected design tradeoffs, as well as unexpected ones, as we work to overcome challenges encountered when trying to map real software to SIMD execution.
988			_aSynthesis Collection of Technology_2015
650		7	_2embne _9686910 _aOrdenadores paralelos
650		7	_2embne _9158747 _aProceso paralelo (Informática)
776	0	8	_iPrinted edition: _z9783031006180
776	0	8	_iPrinted edition: _z9783031028748
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01746-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _eIG _zSI