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| 003 | ES-MaUEC | ||
| 005 | 20230422174623.0 | ||
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| 007 | cr nn 008mamaa | ||
| 008 | 230422s2013 sz | s |||| 0|eng d | ||
| 020 | _a9783031017391 | ||
| 024 | 7 |
_a10.1007/978-3-031-01739-1 _2doi |
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| 040 |
_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC |
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| 050 | 4 |
_aTK7895.M5 _b2013 EB |
|
| 100 | 1 |
_aJanapa Reddi, Vijay _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688223 |
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| 245 | 1 | 0 |
_aResilient Architecture Design for Voltage Variation _cby Vijay Janapa Reddi, Meeta Sharma Gupta |
| 250 | _a1st edition 2013 | ||
| 264 | 1 |
_aCham _bSpringer International Publishing _c2013 |
|
| 300 | _a1 recurso en línea (XVI, 124 páginas) | ||
| 336 |
_atexto _btxt _2rdacontent |
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| 337 |
_aelectrónico _bc _2rdamedia |
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| 338 |
_arecurso electrónico _bcr _2rdacarrier |
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| 347 |
_aarchivo de texto _bPDF |
||
| 490 | 0 |
_aSynthesis Lectures on Computer Architecture _x1935-3243 |
|
| 505 | 0 | _aIntroduction -- Modeling Voltage Variation -- Understanding the Characteristics of Voltage Variation -- Traditional Solutions and Emerging Solution Forecast -- Allowing and Tolerating Voltage Emergencies -- Predicting and Avoiding Voltage Emergencies -- Eliminiating Recurring Voltage Emergencies -- Future Directions on Resiliency. | |
| 520 | _aShrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe the problem of voltage variation and the factors that influence this variation during processor design and operation. We also describe a variety of runtime hardware and software mitigation techniques that either tolerate, avoid, and/or eliminate voltage violations. We hope processor architects will find the information useful since tolerance, avoidance, and elimination are generalizable constructs that can serve as a basis for addressing other reliability challenges as well. Table of Contents: Introduction / Modeling Voltage Variation / Understanding the Characteristics of Voltage Variation / Traditional Solutions and Emerging Solution Forecast / Allowing and Tolerating Voltage Emergencies / Predicting and Avoiding Voltage Emergencies / Eliminiating Recurring Voltage Emergencies / Future Directions on Resiliency. | ||
| 988 | _aSynthesis Collection of Technology_2013 | ||
| 650 | 7 |
_2embne _9141164 _aMicroprocesadores |
|
| 700 | 1 |
_aGupta, Meeta Sharma _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688224 |
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| 776 | 0 | 8 |
_iPrinted edition: _z9783031006111 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028670 |
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01739-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
_2lcc _cLE |
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| 998 |
_b04/2023 _dz _eIG _zSI |
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