000			03810nam a22004215i 4500
999			_c387797 _d387797
001			387797
003			ES-MaUEC
005			20230420093507.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			230420s2010 sz | s |||| 0|eng d
020			_a9783031798153
024	7		_a10.1007/978-3-031-79815-3 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874.58 _b2010 EB
100	1		_aLi, Lun, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688167 _d1970-
245	1	0	_aDigital System Verification : _bA Combined Formal Methods and Simulation Framework _cby Lun Li, Mitchel Thornton
250			_a1st edition 2010
264		1	_aCham _bSpringer International Publishing _c2010
300			_a1 recurso en línea (XIV, 79 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Digital Circuits & Systems _x1932-3174
505	0		_aIntroduction -- Formal Methods Background -- Simulation Approaches -- Integrated Design Validation System -- Conclusion and Summary.
520			_aIntegrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation. Table of Contents: Introduction / Formal Methods Background / Simulation Approaches / Integrated Design Validation System / Conclusion and Summary.
988			_aSynthesis Collection of Technology_2010
650		7	_2embne _9139614 _aCircuitos integrados
650		7	_9667328 _aSistemas informáticos _xVerificación
700	1		_aThornton, Mitchell Aaron _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686469
776	0	8	_iPrinted edition: _z9783031798146
776	0	8	_iPrinted edition: _z9783031798160
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79815-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _eIG _zSI