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008			220601s2009 sz | s |||| 0|eng d
020			_a9783031797859
024	7		_a10.1007/978-3-031-79785-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7868.L6 _b2009 EB
100	1		_aLala, Parag K., _d1948- _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9688005
245	1	3	_aAn Introduction to Logic Circuit Testing _cby Parag K. Lala
250			_a1st edition 2009
264		1	_aCham _bSpringer International Publishing _c2009
300			_a1 recurso en línea (X, 99 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Digital Circuits & Systems _x1932-3174
505	0		_aIntroduction -- Fault Detection in Logic Circuits -- Design for Testability -- Built-in Self-Test -- References.
520			_aAn Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References.
988			_aSynthesis Collection of Technology_2009
650		7	_2embne _9139135 _aCircuitos lógicos
650		7	_2embne _9141102 _aElectrónica digital
650		7	_2embne _9139614 _aCircuitos integrados
776	0	8	_iPrinted edition: _z9783031797842
776	0	8	_iPrinted edition: _z9783031797866
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79785-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _esc _zSI