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008			220601s2008 sz | s |||| 0|eng d
020			_a9783031797767
024	7		_a10.1007/978-3-031-79776-7 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7888.3 _b2008 EB
100	1		_aDavis, Justin _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686467 _c(Information scientist)
245	1	0	_aFinite State Machine Datapath Design, Optimization, and Implementation _cby Justin Davis, Robert Reese
250			_a1st edition 2008
264		1	_aCham _bSpringer International Publishing _c2008
300			_a1 recurso en línea (IX, 113 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Digital Circuits & Systems _x1932-3174
505	0		_aCalculating Maximum Clock Frequency -- Improving Design Performance -- Finite State Machine with Datapath (FSMD) Design -- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
520			_aFinite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
988			_aSynthesis Collection of Technology_2008
650		7	_2embne _9139135 _aCircuitos lógicos _xDiseño
650		7	_2embne _9167668 _aIngeniería de ordenadores
700	1		_aReese, Robert B. _d1958- _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686468 _q(Robert Bryan),
776	0	8	_iPrinted edition: _z9783031797750
776	0	8	_iPrinted edition: _z9783031797774
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79776-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2023 _dz _esc _zSI