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008			220601s2020 sz | s |||| 0|eng d
020			_a9783031017643
024	7		_a10.1007/978-3-031-01764-3 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.M45 _b2020 EB
100	1		_aNagarajan, Vijay _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687882
245	1	2	_aA Primer on Memory Consistency and Cache Coherence _cby Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood
250			_a1st edition 2020
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XX, 276 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aPreface to the Second Edition -- Preface to the First Edition -- Introduction to Consistency and Coherence -- Coherence Basics -- Memory Consistency Motivation and Sequential Consistency -- Total Store Order and the \lowercase {X -- Relaxed Memory Consistency -- Coherence Protocols -- Snooping Coherence Protocols -- Directory Coherence Protocols -- Advanced Topics in Coherence -- Consistency and Coherence for Heterogeneous Systems -- Specifying and Validating Memory Consistency Models and Cache Coherence -- Authors' Biographies .
520			_aMany modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.
988			_aSynthesis Collection of Technology_2020
650		7	_2embne _9673059 _aGestión de memoria
650		7	_2embne _9686837 _aMemoria caché
700	1		_aSorin, Daniel J. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686831
700	1		_aHill, Mark D. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686942 _q(Mark Donald)
700	1		_aWood, David Allen _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686943
776	0	8	_iPrinted edition: _z9783031000614
776	0	8	_iPrinted edition: _z9783031006364
776	0	8	_iPrinted edition: _z9783031028922
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01764-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2023 _dz _esc _zSI