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008			220601s2022 sz | o |||| 0|eng d
020			_a9783031792052
024	7		_a10.1007/978-3-031-79205-2 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7895 .M4 _b2022 EB
100	1		_aGogte, Vaibhav _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687669
245	1	2	_aA Primer on Memory Persistency _cby Gogte Vaibhav, Kolli Aasheesh, Wenisch Thomas F.
250			_a1st edition 2022
264		1	_aCham _bSpringer International Publishing _c2022
300			_a1 recurso en línea (XIX, 95 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aPreface -- Acknowledgments -- Persistent Memories -- Data Persistence -- Memory Persistency Models -- Hardware Mechanisms for Atomic Durability -- Programming Persistent Memory Systems -- Conclusion -- Bibliography -- Authors' Biographies.
520			_aThis book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
988			_aSynthesis Collection of Technology_2022
650		7	_2embne _9670359 _aDispositivos de almacenamiento de datos
700	1		_aKolli, Aasheesh _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687670
700	1		_aWenisch, Thomas F. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686857
776	0	8	_iPrinted edition: _z9783031792175
776	0	8	_iPrinted edition: _z9783031791932
776	0	8	_iPrinted edition: _z9783031792298
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79205-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2023 _dz _eb _zSI