000			04772nam a22004335i 4500
999			_c387328 _d387328
001			387328
003			ES-MaUEC
005			20230313201721.0
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007			cr nn 008mamaa
008			220601s2018 sz | s |||| 0|eng d
020			_a9783031020346
024	7		_a10.1007/978-3-031-02034-6 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTP482 _b2018 EB
100	1		_aAshraf, Nabil Shovon, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687308 _d1974-
245	1	0	_aLow Substrate Temperature Modeling Outlook of Scaled n-MOSFET _cby Nabil Shovon Ashraf
250			_a1st edition 2018
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XI, 77 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Emerging Engineering Technologies _x2381-1439
505	0		_aPreface -- Acknowledgments -- Introduction -- Historical Perspectives of Scaled MOSFET Evolution -- Simulation Results of On-State Drain Current and Subthreshold Drain Current at Substrate Temperatures Below 300 K -- Simulation Results on Substrate Mobility and On-Channel Mobility of Conventional Long-Channel ??-MOSFET at Substrate Temperatures 300 K and below -- Simulation Outcomes of Subthreshold Slope Factor or Coefficient for Different Substrate Temperatures at the Vicinity of a Subthreshold Region to Deep Subthreshold Region of a Long-Channel ??-MOSFET -- Review of Scaled Device Architectures for Their Feasibility To Low-Temperature Operation Simulation Perspectives of the Author's Current Research -- Summary of Research Results and Conclusions -- References -- Author's Biography.
520			_aLow substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.
988			_aSynthesis Collection of Technology_2018
650		7	_2embne _9674511 _aCriogenia
650		7	_2embne _9162208 _aTransistores de efecto de campo
650		7	_2embne _9140004 _aSemiconductores
776	0	8	_iPrinted edition: _z9783031001406
776	0	8	_iPrinted edition: _z9783031009068
776	0	8	_iPrinted edition: _z9783031031625
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-02034-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2023 _dz _esc _zSI