000			03662nam a22004215i 4500
999			_c387325 _d387325
001			387325
003			ES-MaUEC
005			20230313195609.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			220601s2016 sz | s |||| 0|eng d
020			_a9783031020308
024	7		_a10.1007/978-3-031-02030-8 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050			_aTK7895.M4 _b2016 EB
100	1		_aYu, Shimeng _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687303 _c(Electrical engineer)
245	1	0	_aResistive Random Access Memory (RRAM) _cby Shimeng Yu
250			_a1st edition 2016
264		1	_aCham _bSpringer International Publishing _c2016
300			_a1 recurso en línea (VII, 71 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Emerging Engineering Technologies _x2381-1439
505	0		_aIntroduction to RRAM Technology -- RRAM Device Fabrication and Performances -- RRAM Characterization and Modeling -- RRAM Array Architecture -- Outlook for RRAM's Applications -- Bibliography -- Author Biography.
520			_aRRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM's potential novel applications beyond the NVM applications.
988			_aSynthesis Collection of Technology_2016
650		7	_2embne _9670359 _aDispositivos de almacenamiento de datos
650		7	_2embne _9673059 _aGestión de memoria
650		7	_2embne _9144554 _aArquitectura de ordenador
776	0	8	_iPrinted edition: _z9783031009020
776	0	8	_iPrinted edition: _z9783031031588
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-02030-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2022 _dz _esc _zSI