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008			220601s2020 sz | s |||| 0|eng d
020			_a9783031017674
024	7		_a10.1007/978-3-031-01767-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQ325.5 _b2020 EB
100	1		_aKrishna, Tushar _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686873
245	1	0	_aData Orchestration in Deep Learning Accelerators _cby Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar
250			_a1st edition 2020
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XVII, 146 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aPreface -- Acknowledgments -- Introduction to Data Orchestration -- Dataflow and Data Reuse -- Buffer Hierarchies -- Networks-on-Chip -- Putting it Together: Architecting a DNN Accelerator -- Modeling Accelerator Design Space -- Orchestrating Compressed-Sparse Data -- Conclusions -- Bibliography -- Authors' Biographies.
520			_aThis Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore's Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.
988			_aSynthesis Collection of Technology_2020
650		7	_2embne _9678664 _aRedes neuronales artificiales
650		7	_2embne _9166090 _aAprendizaje automático
650		7	_2embne _9141180 _aProceso de datos
700	1		_aKwon, Hyoukjun _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686905
700	1		_aParashar, Angshuman _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686906
700	1		_aPellauer, Michael _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686907
700	1		_aSamajdar, Ananda _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iPrinted edition: _z9783031000645
776	0	8	_iPrinted edition: _z9783031006395
776	0	8	_iPrinted edition: _z9783031028953
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01767-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2023 _dz _esc _zSI