000			03002nam a22004215i 4500
999			_c387227 _d387227
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003			ES-MaUEC
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007			cr nn 008mamaa
008			220601s2019 sz | s |||| 0|eng d
020			_a9783031017636
024	7		_a10.1007/978-3-031-01763-6 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.M45 _b2019 EB
100	1		_aBalasubramonian, Rajeev, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686836 _d1977-
245	1	0	_aInnovations in the Memory System _cby Rajeev Balasubramonian
250			_a1st edition 2019
264		1	_aCham _bSpringer International Publishing _c2019
300			_a1 recurso en línea (XXI, 129 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aList of Figures -- List of Tables -- Preface -- Acknowledgments -- Introduction -- Memory System Basics for Every Architect -- Commercial Memory Products -- Memory Scheduling -- Data Placement -- Memory Chip Microarchitectures -- Memory Channels -- Memory Reliability -- Memory Refresh -- Near Data Processing -- Memory Security -- Closing Thoughts -- Bibliography -- Author's Biography.
520			_aThe memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
988			_aSynthesis Collection of Technology_2019
650		7	_2embne _9673059 _aGestión de memoria
650		7	_2embne _9453538 _aArquitectura de software
776	0	8	_iPrinted edition: _z9783031000607
776	0	8	_iPrinted edition: _z9783031006357
776	0	8	_iPrinted edition: _z9783031028915
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01763-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2023 _dz _esc _zSI