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| 001 | 387211 | ||
| 003 | ES-MaUEC | ||
| 005 | 20230213205323.0 | ||
| 006 | a||||fo|||| 00| 0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2012 sz | s |||| 0|eng d | ||
| 020 | _a9783031017353 | ||
| 024 | 7 |
_a10.1007/978-3-031-01735-3 _2doi |
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| 040 |
_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC |
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| 050 | 4 |
_aTK7895.M4 _b2012 EB |
|
| 100 | 1 |
_aMuralimanohar, Naveen _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686839 |
|
| 245 | 1 | 0 |
_aPhase Change Memory : _bFrom Devices to Systems _cby Naveen Muralimanohar, Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran |
| 250 | _a1st edition 2012 | ||
| 264 | 1 |
_aCham _bSpringer International Publishing _c2012 |
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| 300 | _a1 recurso en línea (XIV, 122 páginas) | ||
| 336 |
_atexto _btxt _2rdacontent |
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| 337 |
_aelectrónico _bc _2rdamedia |
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| 338 |
_arecurso electrónico _bcr _2rdacarrier |
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| 347 |
_aarchivo de texto _bPDF |
||
| 490 | 0 |
_aSynthesis Lectures on Computer Architecture _x1935-3243 |
|
| 505 | 0 | _aNext Generation Memory Technologies -- Architecting PCM for Main Memories -- Tolerating Slow Writes in PCM -- Wear Leveling for Durability -- Wear Leveling Under Adversarial Settings -- Error Resilience in Phase Change Memories -- Storage and System Design With Emerging Non-Volatile Memories. | |
| 520 | _aAs conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories / Storage and System Design With Emerging Non-Volatile Memories. | ||
| 988 | _aSynthesis Collection of Technology_2012 | ||
| 650 | 7 |
_2embne _9670359 _aDispositivos de almacenamiento de datos |
|
| 650 | 7 |
_2embne _9673059 _aGestión de memoria |
|
| 650 | 7 |
_2embne _9686840 _aMemorias de semiconductores |
|
| 700 | 1 |
_aQureshi, Moinuddin Khalil Ahmed, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686841 _d1978- |
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| 700 | 1 |
_aGurumurthi, Sudhanva _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686842 |
|
| 700 | 1 |
_aRajendran, Bipin _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686843 |
|
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006074 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028632 |
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01735-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
_2lcc _cLE |
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| 998 |
_b02/2023 _dz _esc _zSI |
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