000			03555nam a22004335i 4500
999			_c387210 _d387210
001			387210
003			ES-MaUEC
005			20230213202839.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			220601s2011 sz | s |||| 0|eng d
020			_a9783031017346
024	7		_a10.1007/978-3-031-01734-6 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7895.M4 _b2011 EB
100	1		_aBalasubramonian, Rajeev, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686836 _d1977-
245	1	0	_aMulti-Core Cache Hierarchies _cby Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar
250			_a1st edition 2011
264		1	_aCham _bSpringer International Publishing _c2011
300			_a1 recurso en línea (XVI, 137 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aBasic Elements of Large Cache Design -- Organizing Data in CMP Last Level Caches -- Policies Impacting Cache Hit Rates -- Interconnection Networks within Large Caches -- Technology -- Concluding Remarks.
520			_aA key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks.
988			_aSynthesis Collection of Technology_2011
650		7	_2embne _9686837 _aMemoria caché
650		7	_2embne _9144554 _aArquitectura de ordenador
700	1		_aJouppi, Norman P. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686838 _q(Norman Paul)
700	1		_aMuralimanohar, Naveen _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686839
776	0	8	_iPrinted edition: _z9783031006067
776	0	8	_iPrinted edition: _z9783031028625
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01734-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2023 _dz _esc _zSI