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008			220601s2011 sz | s |||| 0|eng d
020			_a9783031017292
024	7		_a10.1007/978-3-031-01729-2 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.A73 _b2011 EB
100	1		_aGonzález, Antonio _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686833 _q(Antonio M. González Colás)
245	1	0	_aProcessor Microarchitecture : _bAn Implementation Perspective _cby Antonio Gonzalez, Fernando Latorre, Grigorios Magklis
250			_a1st edition 2011
264		1	_aCham _bSpringer International Publishing _c2011
300			_a1 recurso en línea (X, 106 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aIntroduction -- Caches -- The Instruction Fetch Unit -- Decode -- Allocation -- The Issue Stage -- Execute -- The Commit Stage -- References -- Author Biographies.
520			_aThis lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular support to decoding x86 instructions. The next chapter presents the allocation stage and pays special attention to the implementation of register renaming. Afterward, the issue stage is studied. Here, the logic to implement out-of-order issue for both memory and non-memory instructions is thoroughly described. The following chapter focuses on the instruction execution and describes the different functional units that can be found in contemporary microprocessors, as well as the implementation of the bypass network, which has an important impact on the performance. Finally, the lecture concludes with the commit stage, where it describes how the architectural state is updated and recovered in case of exceptions or misspeculations. This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture. It is also intended for practitioners in the industry in the area of microprocessor design. The book assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execution, cache memories, and virtual memory. Table of Contents: Introduction / Caches / The Instruction Fetch Unit / Decode / Allocation / The Issue Stage / Execute / The Commit Stage / References / Author Biographies.
988			_aSynthesis Collection of Technology_2011
650		7	_2embne _9141164 _aMicroprocesadores _xDiseño y construcción
650		7	_2embne _9144554 _aArquitectura de ordenador
700	1		_aLatorre, Fernando _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686834
700	1		_aMagklis, Grigorios, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686835 _d1976-
776	0	8	_iPrinted edition: _z9783031006012
776	0	8	_iPrinted edition: _z9783031028571
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01729-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2023 _dz _esc _zSI