000			03707nam a22004335i 4500
999			_c387205 _d387205
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007			cr nn 008mamaa
008			220601s2008 sz | s |||| 0|eng d
020			_a9783031017216
024	7		_a10.1007/978-3-031-01721-6 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.A73 _b2008 EB
100	1		_aKaxiras, Stefanos _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686829
245	1	0	_aComputer Architecture Techniques for Power-Efficiency _cby Stefanos Kaxiras, Margaret Martonosi
250			_a1st edition 2008
264		1	_aCham _bSpringer International Publishing _c2008
300			_a1 recurso en línea (XI, 207 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Computer Architecture _x1935-3243
505	0		_aIntroduction -- Modeling, Simulation, and Measurement -- Using Voltage and Frequency Adjustments to Manage Dynamic Power -- Optimizing Capacitance and Switching Activity to Reduce Dynamic Power -- Managing Static (Leakage) Power -- Conclusions.
520			_aIn the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions.
988			_aSynthesis Collection of Technology_2008
650		7	_2embne _9148602 _aAhorro de energía
650		7	_2embne _9144554 _aArquitectura de ordenador
650		7	_2embne _9167668 _aIngeniería de ordenadores
700	1		_aMartonosi, Margaret _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686830
776	0	8	_iPrinted edition: _z9783031005930
776	0	8	_iPrinted edition: _z9783031028496
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-01721-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b02/2023 _dz _esc _zSI