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008			220601s2013 sz | s |||| 0|eng d
020			_a9783031798559
024	7		_a10.1007/978-3-031-79855-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQC176.8.N35 _b2013 EB
100	1		_aYanushkevich, Svetlana N. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686478
245	1	0	_aIntroduction to Noise-Resilient Computing _cby Svetlana N. Yanushkevich, Seiya Kasai, Golam Tangim, A.H. Tran
250			_a1st edition 2013
264		1	_aCham _bSpringer International Publishing _c2013
300			_a1 recurso en línea (XIX, 132 páginas)
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
490	0		_aSynthesis Lectures on Digital Circuits & Systems _x1932-3174
505	0		_aIntroduction to probabilistic computation models -- Nanoscale circuits and fluctuation problems -- Estimators and Metrics -- MRF Models of Logic Gates -- Neuromorphic models -- Noise-tolerance via error correcting -- Conclusion and future work.
520			_aNoise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work.
988			_aSynthesis Collection of Technology_2013
650		7	_2embne _9668452 _aTolerancia a los fallos (Informática)
700	1		_aKasai, Seiya _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686479
700	1		_aTangim, Golam _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9686480
700	1		_aTran, A. H. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9687806
776	0	8	_iPrinted edition: _z9783031798542
776	0	8	_iPrinted edition: _z9783031798566
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-031-79855-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2023 _dz _esc _zSI