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007			cr nn 008mamaa
008			230112s2022 sz | s |||| 0|eng d
020			_a9783030981129
024	7		_a10.1007/978-3-030-98112-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7895.E42 _b2022 EB
100	1		_aChakravarthi, Veena S. _eautor _0(orcid)0000-0002-8703-2376 _1https://orcid.org/0000-0002-8703-2376 _4aut _4http://id.loc.gov/vocabulary/relators/aut _9671581
245	1	0	_aSoC Physical Design _bA Comprehensive Guide / _cby Veena S. Chakravarthi, Shivananda R. Koteshwar.
250			_a1st edition 2022
264		1	_aCham _bSpringer International Publishing _c2022
300			_a1 recurso en línea (XXIV, 155 páginas) _b106 ilustraciones, 80 ilustraciones a color
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
505	0		_aIntroduction -- SoC Physical Design Flow and Algorithms -- Physical Design Floor Plan and Placement -- Clock, Reset, and HFN -- Physical Design Routing -- Physical Design Verification.
520			_aSoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Provides a comprehensive overview of the skills required for complex SoC design and development; Examines SOC design challenges in nanotechnology scales; Offers readers professional "tricks" to using tools for optimal design runs.
988			_aSpringer_Engineering_2022
650		7	_2embne _9667201 _aSistemas embebidos
650		7	_2embne _9139614 _aCircuitos integrados
700	1		_aKoteshwar, Shivananda R. _eautor _0(orcid)0000-0003-4299-4069 _1https://orcid.org/0000-0003-4299-4069 _4aut _4http://id.loc.gov/vocabulary/relators/aut _9685942
776	0	8	_iPrinted edition: _z9783030981112
776	0	8	_iPrinted edition: _z9783030981136
776	0	8	_iPrinted edition: _z9783030981143
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-98112-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2023 _dz _eIG _zSI