000			04264nam a22004335i 4500
999			_c383042 _d383042 _x1
001			383042
003			ES-MaUEC
005			20230102122035.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			221022s2022 sz | s |||| 0|eng d
020			_a9783030871819
024	7		_a10.1007/978-3-030-87181-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aQA76.9.F67 _b2022 EB
100	1		_aRussinoff, David, _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9685022 _d1948-
245	1	0	_aFormal Verification of Floating-Point Hardware Design : _ba Mathematical Approach _cby David M. Russinoff
250			_aSecond edition 2022
264		1	_aCham _bSpringer International Publising _c2022
300			_a1 recurso en línea (XXVIII, 436 páginas) _b40 ilustraciones
336			_atexto _btxt _2rdacontent
337			_aelectrónico _bc _2rdamedia
338			_arecurso electrónico _bcr _2rdacarrier
347			_aarchivo de texto _bPDF
505	0		_aPart I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor.
520			_aThis is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I-III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.
988			_aSpringer_Computer_2022
650		7	_2embne _9154256 _aLenguajes formales
650		7	_2embne _9138647 _aAritmética
650		7	_2embne _9405008 _aMatemáticas
776	0	8	_iPrinted edition: _z9783030871802
776	0	8	_iPrinted edition: _z9783030871826
776	0	8	_iPrinted edition: _z9783030871833
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-87181-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b10/2022 _dz _eIG _zSI