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008			220127s2021 sz | s |||| 0|eng d
020			_a9783030692094
024	7		_a10.1007/978-3-030-69209-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874 _b2021 EB
100	1		_aHuhn, Sebastian _eautor _4 _4http://id.loc.gov/vocabulary/relators/aut _9681276 _d1974-
245	1	0	_aDesign for Testability, Debug and Reliability : _bNext Generation Measures Using Formal Techniques _cby Sebastian Huhn, Rolf Drechsler
250			_aFirst edition 2021
264		1	_aCham _bSpringer International Publishing _c2021
300			_a1 recurso en línea (XXI, 164 páginas) _b 47 ilustraciones, 25 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aarchivo de texto _bPDF
490	0		_aEngineering (SpringerNature-11647)
490	0		_aEngineering (R0) (SpringerNature-43712)
505	0		_aIntroduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.
520	3		_aThis book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.
988			_aSpringer_Engineering_2021
650		7	_2embne _9179611 _aCircuitos integrados _xDiseño y construcción
650		7	_2embne _9670306 _aDepuración (Informática)
700	1		_aDrechsler, Rolf _eautor _4 _4http://id.loc.gov/vocabulary/relators/aut _999112
776	0	8	_iPrinted edition: _z9783030692087
776	0	8	_iPrinted edition: _z9783030692100
776	0	8	_iPrinted edition: _z9783030692117
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-69209-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2022 _dz _eIG _zSI