000			04162nam a22004215i 4500
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008			220118s2021 gw | s |||| 0|eng d
020			_a9783030713195
024	7		_a10.1007/978-3-030-71319-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7885.7 _b2021 EB
100			_aMehta, Ashok B. _eautor _4http://id.loc.gov/vocabulary/relators/aut _998903
245	1	0	_aIntroduction to SystemVerilog _cby Ashok B. Mehta
250			_aFirst edition 2021
264		1	_aCham _bSpringer International Publishing _c2021
300			_a1 recurso en línea (XXXV, 852 páginas) _b 156 ilustraciones, 148 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aarchivo de texto _bPDF
490	0		_aEngineering (SpringerNature-11647)
490	0		_aEngineering (R0) (SpringerNature-43712)
505	0		_aIntroduction -- Data Types -- Arrays -- Queues -- Structures -- Packages -- Class -- SystemVerilog 'module' -- SystemVerilog 'program' -- Interfaces -- Operators -- Constrained Random Test Generation and Verification -- SystemVerilog Assertions -- Functional Coverage -- SystemVerilog Processes -- Procedural programming statements -- Processes -- Tasks and Functions -- Clocking Blocks -- Checkers -- Inter-process communication and synchronization -- Utility System tasks and functions.
520	3		_aThis book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems.
988			_aSpringer_Engineering_2021
650		7	_2embne _9668846 _aVERILOG (Lenguaje de descripción del soporte físico)
650		7	_2embne _9150789 _aLenguajes de descripción del soporte físico
776	0	8	_iPrinted edition: _z9783030713188
776	0	8	_iPrinted edition: _z9783030713201
776	0	8	_iPrinted edition: _z9783030713218
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-71319-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2022 _dz _eIG _zSI