000			04027nam a22004455i 4500
999			_c361782 _d361782 _x1
001			361782
003			ES-MaUEC
005			20230102121428.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			220112s2021 sz | s |||| 0|eng d
020			_a9783030683689
024	7		_a10.1007/978-3-030-68368-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7871.95 _b2021 EB
100	1		_aZimpeck, Alexandra _eautor _9680487
245	1	0	_aMitigating Process Variability and Soft Errors at Circuit-Level for FinFETs _cby Alexandra Zimpeck, Cristina Meinhardt, Laurent Artola, Ricardo Reis
250			_aFirst edition 2021
264		1	_aCham _bSpringer International Publishing _c2021
300			_a1 recurso en línea (XIII, 131 páginas) _b 89 ilustraciones, 86 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aarchivo de texto _bPDF
490	0		_aEngineering (SpringerNature-11647)
490	0		_aEngineering (R0) (SpringerNature-43712)
505	0		_aChapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.
520	3		_aThis book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.
988			_aSpringer_Engineering_2021
650		7	_2embne _9162208 _aTransistores de efecto de campo
700	1		_aMeinhardt, Cristina _eautor _9680488
700	1		_aArtola, Laurent _eautor _9680489
700	1		_aReis, Ricardo _eautor _9100026
776	0	8	_iPrinted edition: _z9783030683672
776	0	8	_iPrinted edition: _z9783030683696
776	0	8	_iPrinted edition: _z9783030683702
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-68368-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2022 _dz _eIG _zSI