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020			_a9783030816414
024	7		_a10.1007/978-3-030-81641-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874.75 _b2021 EB
245	0	0	_aVLSI-SoC : _bDesign Trends : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers _cedited by Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
250			_aFirst edition 2021
264		1	_aCham _bSpringer International Publising _c2021
300			_a1 recurso en línea (XVIII, 364 páginas) _b209 ilustraciones, 139 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aarchivo de texto _bPDF
490	0		_aIFIP Advances in Information and Communication Technology _x1868-4238 _v621
490	0		_aComputer Science (SpringerNature-11645)
490	0		_aComputer Science (R0) (SpringerNature-43710)
505	0		_aLow-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI -- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP -- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring -- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation -- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform -- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array -- Learning Based Timing Closure on Relative Timed Design -- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication -- From Informal Specifications to an ABV Framework for Industrial Firmware Verification -- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs -- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique -- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption -- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs -- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model -- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics -- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory
520	3		_aThis book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
988			_aSpringer_Computer_2021
650		7	_2embne _9669585 _aCircuitos integrados VLSI _xDiseño _vCongresos y asambleas
650		7	_2embne _9483083 _aInternet de los objetos _vCongresos y asambleas
700	1		_aCalimera, Andrea _eeditor literario _0(orcid)0000-0001-5881-3811 _1https://orcid.org/0000-0001-5881-3811 _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aGaillardon, Pierre-Emmanuel _eeditor literario
700	1		_aKorgaonkar, Kunal _eeditor literario
700	1		_aKvatinsky, Shahar _eeditor literario
700	1		_aReis, Ricardo _eeditor literario
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-81641-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b01/2022 _dz _eu _zSI